Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1364314631	33040884	0	0
intr_enable_rd_A	1364314631	14816	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1364314631	33040884	0	0
T14	14289	3	0	0
T15	4545	746	0	0
T16	17780	1013	0	0
T17	1971	0	0	0
T18	1963	0	0	0
T19	1427	0	0	0
T20	14999	1275	0	0
T21	2215	5	0	0
T22	1669	2	0	0
T23	0	5	0	0
T24	0	785	0	0
T28	1010	0	0	0
T63	0	6	0	0
T64	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1364314631	14816	0	0
T13	1337	23	0	0
T14	14289	0	0	0
T15	4545	0	0	0
T16	17780	0	0	0
T17	1971	0	0	0
T18	1963	0	0	0
T19	1427	0	0	0
T20	14999	0	0	0
T21	2215	0	0	0
T22	1669	3	0	0
T64	0	177	0	0
T69	0	40	0	0
T70	0	18	0	0
T71	0	3	0	0
T72	0	17	0	0
T73	0	26	0	0
T74	0	43	0	0
T75	0	20	0	0