Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

157880702

1

T12

957

T13

170

T14

26

full_word

122141970

1

T12

984

T13

98

T14

14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	280022242	1			T12	1941		T13	268		T14	40
auto[TlIntgErrCmd]	131	1			T15	3		T19	6		T60	14
auto[TlIntgErrData]	167	1			T15	16		T19	14		T60	9
auto[TlIntgErrBoth]	132	1			T15	11		T19	10		T60	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108800459

1

T12

1869

T13

74

T14

20

auto[1]

171222213

1

T12

72

T13

194

T14

20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	65059178	1			T12	946		T13	36		T14	11
auto[TlIntgErrNone]	partial	auto[1]	92821133	1			T12	11		T13	134		T14	15
auto[TlIntgErrNone]	full_word	auto[0]	43741091	1			T12	923		T13	38		T14	9
auto[TlIntgErrNone]	full_word	auto[1]	78400840	1			T12	61		T13	60		T14	5
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T15	2		T19	3		T60	5
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T15	1		T19	3		T60	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T60	1		T136	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T60	4		T61	2		T135	2
auto[TlIntgErrData]	partial	auto[0]	78	1			T15	9		T19	7		T60	1
auto[TlIntgErrData]	partial	auto[1]	73	1			T15	6		T19	6		T60	5
auto[TlIntgErrData]	full_word	auto[0]	10	1			T15	1		T60	1		T74	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T19	1		T60	2		T137	2
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T15	4		T19	5		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T15	6		T19	5		T60	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T138	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T15	1		T61	1		T137	1