Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	108429580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123168778

1

T14

425

T15

15

T16

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90991940	1			T14	138		T15	20		T16	20
values[0x0]	65278718	1			T14	161		T15	8		T16	10
values[0x1]	75327700	1			T14	202		T15	12		T16	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	79336011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152262347

1

T14

467

T15

18

T16

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	830006	1			T14	4		T17	5		T21	8
valid_sources[0x01]	900483	1			T14	2		T17	2		T20	3
valid_sources[0x02]	827379	1			T17	3		T20	4		T21	1
valid_sources[0x03]	910310	1			T14	2		T17	1		T20	3
valid_sources[0x04]	850555	1			T21	6		T23	1		T69	1
valid_sources[0x05]	853983	1			T14	4		T17	2		T20	3
valid_sources[0x06]	852808	1			T17	1		T18	3		T20	2
valid_sources[0x07]	816560	1			T14	2		T17	1		T20	4
valid_sources[0x08]	834377	1			T14	3		T17	1		T21	2
valid_sources[0x09]	856130	1			T14	2		T17	1		T20	2
valid_sources[0x0a]	844513	1			T14	3		T17	1		T20	2
valid_sources[0x0b]	845134	1			T14	1		T17	3		T20	4
valid_sources[0x0c]	878551	1			T14	2		T17	3		T20	2
valid_sources[0x0d]	874307	1			T14	3		T17	6		T20	2
valid_sources[0x0e]	878605	1			T14	1		T17	2		T20	7
valid_sources[0x0f]	840084	1			T14	1		T15	1		T20	2
valid_sources[0x10]	1265855	1			T14	2		T17	2		T20	3
valid_sources[0x11]	880376	1			T14	1		T17	1		T19	5
valid_sources[0x12]	884349	1			T17	1		T20	1		T21	2
valid_sources[0x13]	839965	1			T14	3		T15	1		T17	2
valid_sources[0x14]	840237	1			T15	1		T17	4		T20	4
valid_sources[0x15]	866022	1			T14	2		T17	4		T20	2
valid_sources[0x16]	847211	1			T14	5		T15	2		T20	3
valid_sources[0x17]	1252304	1			T14	1		T17	1		T20	2
valid_sources[0x18]	849928	1			T14	2		T17	1		T20	2
valid_sources[0x19]	854824	1			T14	3		T17	2		T20	5
valid_sources[0x1a]	893653	1			T14	2		T17	1		T20	4
valid_sources[0x1b]	852449	1			T14	1		T17	2		T20	4
valid_sources[0x1c]	832198	1			T14	4		T17	1		T20	2
valid_sources[0x1d]	986830	1			T14	4		T17	1		T20	2
valid_sources[0x1e]	1287345	1			T14	2		T17	3		T18	1
valid_sources[0x1f]	860236	1			T14	2		T20	5		T21	2
valid_sources[0x20]	837440	1			T14	3		T17	5		T20	3
valid_sources[0x21]	951489	1			T17	4		T20	3		T21	2
valid_sources[0x22]	860973	1			T14	1		T17	1		T21	3
valid_sources[0x23]	853889	1			T14	3		T17	3		T20	3
valid_sources[0x24]	839884	1			T14	2		T20	2		T21	6
valid_sources[0x25]	848619	1			T14	2		T17	2		T18	1
valid_sources[0x26]	845948	1			T14	1		T17	1		T20	3
valid_sources[0x27]	858542	1			T14	4		T17	3		T18	1
valid_sources[0x28]	833464	1			T17	4		T21	8		T23	1
valid_sources[0x29]	859163	1			T14	3		T17	2		T20	1
valid_sources[0x2a]	816477	1			T14	1		T15	1		T17	1
valid_sources[0x2b]	822813	1			T14	4		T17	3		T20	2
valid_sources[0x2c]	819245	1			T14	1		T17	3		T20	1
valid_sources[0x2d]	851736	1			T14	3		T17	1		T20	1
valid_sources[0x2e]	893299	1			T14	3		T20	1		T21	3
valid_sources[0x2f]	1203841	1			T17	4		T20	3		T21	2
valid_sources[0x30]	1268488	1			T14	1		T17	1		T20	2
valid_sources[0x31]	858418	1			T14	3		T17	1		T19	10
valid_sources[0x32]	929968	1			T17	2		T20	4		T21	4
valid_sources[0x33]	919433	1			T14	1		T17	2		T20	3
valid_sources[0x34]	846161	1			T14	1		T17	2		T20	3
valid_sources[0x35]	856104	1			T14	1		T17	6		T20	3
valid_sources[0x36]	858428	1			T14	1		T17	1		T20	2
valid_sources[0x37]	1234060	1			T14	1		T17	1		T18	3
valid_sources[0x38]	850821	1			T14	1		T17	2		T21	6
valid_sources[0x39]	856874	1			T14	2		T20	4		T21	1
valid_sources[0x3a]	849213	1			T14	4		T17	2		T20	2
valid_sources[0x3b]	854234	1			T14	5		T17	2		T20	1
valid_sources[0x3c]	867285	1			T14	1		T17	1		T20	1
valid_sources[0x3d]	837524	1			T17	4		T20	4		T21	7
valid_sources[0x3e]	855121	1			T14	2		T17	2		T20	2
valid_sources[0x3f]	842306	1			T14	1		T17	2		T20	1
valid_sources[0x40]	846884	1			T14	4		T17	2		T20	1
valid_sources[0x41]	1215220	1			T14	1		T17	5		T20	1
valid_sources[0x42]	881006	1			T14	2		T17	1		T20	3
valid_sources[0x43]	875697	1			T14	3		T17	4		T20	3
valid_sources[0x44]	879088	1			T14	2		T15	1		T20	3
valid_sources[0x45]	852470	1			T14	1		T17	5		T20	2
valid_sources[0x46]	890647	1			T14	2		T15	1		T17	3
valid_sources[0x47]	834288	1			T14	5		T17	1		T21	2
valid_sources[0x48]	818800	1			T17	4		T21	3		T22	2
valid_sources[0x49]	840680	1			T14	2		T17	3		T21	3
valid_sources[0x4a]	835047	1			T14	2		T17	1		T18	3
valid_sources[0x4b]	840587	1			T17	6		T20	2		T21	5
valid_sources[0x4c]	1247016	1			T14	2		T17	2		T19	3
valid_sources[0x4d]	849979	1			T14	1		T17	2		T20	1
valid_sources[0x4e]	851500	1			T14	1		T20	1		T21	2
valid_sources[0x4f]	1159684	1			T14	2		T17	5		T21	6
valid_sources[0x50]	851744	1			T14	2		T17	2		T18	1
valid_sources[0x51]	860078	1			T14	3		T17	1		T18	1
valid_sources[0x52]	869739	1			T14	2		T17	1		T21	7
valid_sources[0x53]	867817	1			T14	1		T17	5		T19	3
valid_sources[0x54]	1268178	1			T14	2		T19	3		T21	1
valid_sources[0x55]	849737	1			T14	3		T20	1		T21	3
valid_sources[0x56]	857546	1			T14	2		T18	4		T20	1
valid_sources[0x57]	836560	1			T14	3		T17	2		T72	3
valid_sources[0x58]	814970	1			T14	4		T20	1		T21	4
valid_sources[0x59]	1289137	1			T14	5		T17	1		T20	2
valid_sources[0x5a]	854191	1			T14	1		T15	3		T17	5
valid_sources[0x5b]	857861	1			T14	1		T17	2		T21	3
valid_sources[0x5c]	868079	1			T14	1		T17	4		T20	1
valid_sources[0x5d]	1196133	1			T14	1		T17	1		T20	6
valid_sources[0x5e]	1273628	1			T17	3		T20	2		T21	8
valid_sources[0x5f]	861267	1			T14	3		T17	1		T20	2
valid_sources[0x60]	1233482	1			T17	4		T20	2		T21	3
valid_sources[0x61]	887110	1			T14	2		T20	1		T22	8
valid_sources[0x62]	844927	1			T14	5		T18	1		T20	5
valid_sources[0x63]	867878	1			T15	1		T17	1		T20	1
valid_sources[0x64]	846338	1			T14	1		T17	1		T20	2
valid_sources[0x65]	815447	1			T20	4		T21	4		T22	3
valid_sources[0x66]	881636	1			T14	1		T17	2		T18	1
valid_sources[0x67]	858326	1			T14	3		T16	40		T17	2
valid_sources[0x68]	824521	1			T14	6		T17	7		T21	6
valid_sources[0x69]	820242	1			T14	1		T17	2		T20	3
valid_sources[0x6a]	854010	1			T14	1		T17	3		T20	2
valid_sources[0x6b]	895804	1			T14	2		T17	2		T18	1
valid_sources[0x6c]	847624	1			T14	3		T17	3		T21	1
valid_sources[0x6d]	846844	1			T14	4		T18	1		T20	2
valid_sources[0x6e]	1612608	1			T14	1		T17	3		T20	1
valid_sources[0x6f]	845971	1			T14	2		T17	6		T18	3
valid_sources[0x70]	848218	1			T14	3		T17	3		T20	1
valid_sources[0x71]	816247	1			T14	2		T17	3		T21	2
valid_sources[0x72]	857042	1			T14	1		T21	4		T23	1
valid_sources[0x73]	874125	1			T14	1		T17	1		T20	5
valid_sources[0x74]	855175	1			T14	6		T15	2		T20	1
valid_sources[0x75]	851667	1			T14	1		T15	4		T17	1
valid_sources[0x76]	841867	1			T14	2		T17	2		T20	2
valid_sources[0x77]	818939	1			T14	4		T17	1		T18	2
valid_sources[0x78]	889813	1			T14	2		T17	2		T20	2
valid_sources[0x79]	891425	1			T14	1		T17	3		T20	1
valid_sources[0x7a]	819080	1			T14	3		T17	9		T20	2
valid_sources[0x7b]	1288064	1			T14	3		T17	1		T21	8
valid_sources[0x7c]	842744	1			T17	1		T20	1		T21	5
valid_sources[0x7d]	810797	1			T14	1		T15	3		T17	1
valid_sources[0x7e]	835734	1			T14	3		T17	1		T20	1
valid_sources[0x7f]	869648	1			T14	4		T20	1		T21	7
valid_sources[0x80]	870632	1			T17	3		T20	1		T21	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44281840

1

T14

109

T15

10

T16

9

values[0x0]

all_enables

biggest_size

41080549

1

T14

159

T15

4

T16

3

values[0x1]

all_enables

biggest_size

37806389

1

T14

157

T15

1

T16

3