Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

164381070

1

T14

1586

T15

25

T16

25

full_word

127390858

1

T14

550

T15

15

T16

15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	291771488	1			T14	2136		T15	40		T16	40
auto[TlIntgErrCmd]	154	1			T20	2		T21	8		T66	11
auto[TlIntgErrData]	145	1			T20	5		T21	6		T66	9
auto[TlIntgErrBoth]	141	1			T20	3		T21	6		T66	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113067658

1

T14

566

T15

20

T16

20

auto[1]

178704270

1

T14

1570

T15

20

T16

20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	67105742	1			T14	424		T15	10		T16	11
auto[TlIntgErrNone]	partial	auto[1]	97274926	1			T14	1162		T15	15		T16	14
auto[TlIntgErrNone]	full_word	auto[0]	45961723	1			T14	142		T15	10		T16	9
auto[TlIntgErrNone]	full_word	auto[1]	81429097	1			T14	408		T15	5		T16	6
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T20	1		T21	4		T66	6
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T20	1		T21	4		T66	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T151	1		T152	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T153	1		T147	2		T67	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T20	2		T21	3		T66	3
auto[TlIntgErrData]	partial	auto[1]	62	1			T20	2		T21	3		T66	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T153	1		T147	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T20	1		T66	2		T75	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T21	1		T66	5		T155	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T20	3		T21	5		T66	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T75	1		T68	1		T67	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T77	2		T68	2		T147	1