Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1482213739	36573941	0	0
intr_enable_rd_A	1482213739	12852	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482213739	36573941	0	0
T14	5273	1070	0	0
T15	1091	0	0	0
T16	1352	0	0	0
T17	2060	0	0	0
T18	1310	0	0	0
T19	1382	0	0	0
T20	5330	4	0	0
T21	11320	5	0	0
T22	2839	0	0	0
T23	2802	186	0	0
T24	0	2	0	0
T25	0	705	0	0
T26	0	2	0	0
T27	0	1111	0	0
T28	0	513	0	0
T66	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482213739	12852	0	0
T18	1310	48	0	0
T19	1382	22	0	0
T20	5330	46	0	0
T21	11320	179	0	0
T22	2839	32	0	0
T23	2802	0	0	0
T29	0	4	0	0
T66	0	224	0	0
T69	1579	25	0	0
T70	0	34	0	0
T71	0	48	0	0
T72	904	0	0	0
T73	881	0	0	0
T74	8570	0	0	0