Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

163267212

1

T13

33

T14

28

T15

15

full_word

126034436

1

T13

25

T14

75

T15

38

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	289301258	1			T13	58		T14	103		T15	53
auto[TlIntgErrCmd]	131	1			T51	8		T52	8		T66	5
auto[TlIntgErrData]	120	1			T51	6		T52	6		T66	7
auto[TlIntgErrBoth]	139	1			T51	6		T52	6		T66	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112283814

1

T13

29

T14

55

T15

29

auto[1]

177017834

1

T13

29

T14

48

T15

24

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	67002504	1			T13	16		T14	23		T15	13
auto[TlIntgErrNone]	partial	auto[1]	96264351	1			T13	17		T14	5		T15	2
auto[TlIntgErrNone]	full_word	auto[0]	45281141	1			T13	13		T14	32		T15	16
auto[TlIntgErrNone]	full_word	auto[1]	80753262	1			T13	12		T14	43		T15	22
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T51	2		T52	4		T66	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T51	5		T52	4		T66	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T148	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T51	1		T149	1		T67	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T51	3		T52	1		T66	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T51	2		T52	5		T66	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T51	1		T66	1		T150	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T149	1		T67	1		T147	2
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T51	1		T52	1		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T51	3		T52	5		T66	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T51	2		T67	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T66	1		T150	3		T151	1