Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1389212117	36154739	0	0
intr_enable_rd_A	1389212117	10935	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389212117	36154739	0	0
T16	7867	383	0	0
T17	22265	0	0	0
T18	1329	0	0	0
T19	1131	0	0	0
T20	1143	0	0	0
T21	1540	0	0	0
T22	616059	284060	0	0
T23	12349	741	0	0
T24	1421	0	0	0
T25	0	188	0	0
T26	0	881	0	0
T27	0	748	0	0
T28	0	9	0	0
T32	1179	0	0	0
T51	0	3	0	0
T52	0	4	0	0
T66	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389212117	10935	0	0
T13	1594	43	0	0
T14	959	0	0	0
T15	1026	0	0	0
T16	7867	0	0	0
T17	22265	0	0	0
T18	1329	28	0	0
T19	1131	15	0	0
T20	1143	4	0	0
T21	1540	0	0	0
T22	616059	0	0	0
T66	0	121	0	0
T69	0	13	0	0
T70	0	5	0	0
T71	0	8	0	0
T72	0	5	0	0
T73	0	3	0	0