Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.22	98.47	75.64		90.00	92.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256	100.00	100.00	100.00		100.00	100.00

---

Module Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	100.00		100.00	94.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_prim_sha2_256

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	96.94	100.00	100.00		100.00	87.76

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		131	129	98.47
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	182	11	11	100.00
ALWAYS	202	4	4	100.00
ALWAYS	208	8	8	100.00
ALWAYS	222	3	3	100.00
ALWAYS	228	12	12	100.00
ALWAYS	248	3	3	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
ALWAYS	261	7	7	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	283	1	1	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	296	3	3	100.00
ALWAYS	309	3	3	100.00
ALWAYS	314	26	26	100.00
ALWAYS	365	3	3	100.00
ALWAYS	379	3	3	100.00
CONT_ASSIGN	383	1	1	100.00
ALWAYS	386	23	21	91.30
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	459	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
57	1	1
60	1	1
178	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
194	1	1
196	1	1
			MISSING_ELSE
202	2	2
203	2	2
			==> MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
			MISSING_ELSE
222	2	2
223	1	1
228	1	1
229	1	1
230	1	1
231	1	1
233	1	1
234	1	1
235	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
			MISSING_ELSE
248	2	2
249	1	1
254	8	8
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
269	1	1
271	1	1
			MISSING_ELSE
278	2	2
279	1	1
283	1	1
288	2	2
289	1	1
293	1	1
296	2	2
297	1	1
309	2	2
310	1	1
314	1	1
315	1	1
316	1	1
318	1	1
320	2	2
321	1	1
325	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
334	1	1
335	1	1
340	1	1
341	1	1
343	1	1
344	1	1
345	1	1
347	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
365	2	2
366	1	1
379	2	2
380	1	1
383	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
392	1	1
394	1	1
395	1	1
396	1	1
398	1	1
403	1	1
404	1	1
407	1	1
408	1	1
409	1	1
411	1	1
416	1	1
417	1	1
418	0	1
419	0	1
421	1	1
430	2	2
			MISSING_ELSE
433	1	1
459	1	1

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	78	59	75.64
Logical	78	59	75.64
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       60
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (((!sha_en_i)) || clear_digest)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((((~sha_en_i)) || hash_start_i) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (((~sha_en_i)) || hash_start_i)
                 ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       404
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       404
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       404
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       404
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       404
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       404
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       417
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       430
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       433
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       433
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       433
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       433
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       433
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       459
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_start_i)))
             -----------1-----------    ----------2----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       459
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       459
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	314	Covered	T13
FifoLoadFromFifo	320	Covered	T13
FifoWait	330	Covered	T13

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	320	Covered	T13
FifoLoadFromFifo->FifoIdle	314	Covered	T13
FifoLoadFromFifo->FifoWait	330	Covered	T13
FifoWait->FifoIdle	314	Covered	T13
FifoWait->FifoLoadFromFifo	345	Covered	T13

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	396	Covered	T13
ShaIdle	398	Covered	T13
ShaUpdateDigest	409	Covered	T13

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	430	Covered	T13
ShaCompress->ShaUpdateDigest	409	Covered	T13
ShaIdle->ShaCompress	396	Covered	T13
ShaUpdateDigest->ShaCompress	419	Not Covered
ShaUpdateDigest->ShaIdle	421	Covered	T13

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		69	64	92.75
TERNARY	60	3	3	100.00
TERNARY	283	3	3	100.00
TERNARY	433	3	2	66.67
IF	262	4	4	100.00
IF	278	2	2	100.00
IF	288	2	2	100.00
IF	296	2	2	100.00
IF	309	2	2	100.00
CASE	318	9	8	88.89
IF	356	3	3	100.00
IF	365	2	2	100.00
IF	379	2	2	100.00
CASE	392	8	6	75.00
IF	430	2	2	100.00
IF	183	6	6	100.00
IF	202	3	2	66.67
IF	209	4	4	100.00
IF	222	2	2	100.00
IF	229	5	5	100.00
IF	248	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	(hash_start_i) ? 
-2-:	60	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	(((~sha_en_i) || hash_start_i)) ? 
-2-:	283	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	433	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if (((!sha_en_i) || hash_start_i))
-2-:	264	if (run_hash)
-3-:	265	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	296	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	case (fifo_st_q)
-2-:	320	if (hash_start_i)
-3-:	325	if ((!shaf_rvalid))
-4-:	329	if ((w_index_q == 4'd15))
-5-:	340	if ((msg_feed_complete && one_chunk_done))
-6-:	344	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T1,T2,T3
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T2,T3
FifoWait	-	-	-	1	-	Covered	T1,T2,T3
FifoWait	-	-	-	0	1	Covered	T1,T2,T3
FifoWait	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	356	if ((!sha_en_i))
-2-:	359	if (hash_start_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	case (sha_st_q)
-2-:	394	if ((fifo_st_q == FifoWait))
-3-:	404	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	408	if (one_chunk_done)
-5-:	417	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T2,T3
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T3
ShaCompress	-	0	1	-	Covered	T1,T2,T3
ShaCompress	-	0	0	-	Covered	T1,T2,T3
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	430	if (((!sha_en_i) || hash_start_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (wipe_secret_i)
-2-:	185	if (((!sha_en_i) || hash_start_i))
-3-:	187	if (((!run_hash) && update_w_from_fifo))
-4-:	191	if (calculate_next_w)
-5-:	194	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T2,T3,T5
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	203	if ((!MultimodeEn))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	209	if (wipe_secret_i)
-2-:	213	if (init_hash)
-3-:	215	if (run_hash)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if (wipe_secret_i)
-2-:	233	if (hash_start_i)
-3-:	237	if (((!sha_en_i) || clear_digest))
-4-:	239	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T2,T3,T5
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Line No.	Total	Covered	Percent
TOTAL		129	129	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	182	11	11	100.00
ALWAYS	202	4	4	100.00
ALWAYS	208	8	8	100.00
ALWAYS	222	3	3	100.00
ALWAYS	228	12	12	100.00
ALWAYS	248	3	3	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
ALWAYS	261	7	7	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	283	1	1	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	296	3	3	100.00
ALWAYS	309	3	3	100.00
ALWAYS	314	26	26	100.00
ALWAYS	365	3	3	100.00
ALWAYS	379	3	3	100.00
CONT_ASSIGN	383	1	1	100.00
ALWAYS	386	21	21	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	459	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
57	1	1
60	1	1
178	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
194	1	1
196	1	1
			MISSING_ELSE
202	2	2
203	2	2
			==> MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
			MISSING_ELSE
222	2	2
223	1	1
228	1	1
229	1	1
230	1	1
231	1	1
233	1	1
234	1	1
235	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
			MISSING_ELSE
248	2	2
249	1	1
254	8	8
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
269	1	1
271	1	1
			MISSING_ELSE
278	2	2
279	1	1
283	1	1
288	2	2
289	1	1
293	1	1
296	2	2
297	1	1
309	2	2
310	1	1
314	1	1
315	1	1
316	1	1
318	1	1
320	2	2
321	1	1
325	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
334	1	1
335	1	1
340	1	1
341	1	1
343	1	1
344	1	1
345	1	1
347	1	1
			Exclude Annotation: VC_COV_UNR
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
365	2	2
366	1	1
379	2	2
380	1	1
383	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
392	1	1
394	1	1
395	1	1
396	1	1
398	1	1
403	1	1
404	1	1
407	1	1
408	1	1
409	1	1
411	1	1
416	1	1
417	1	1
418		excluded
			Exclude Annotation: VC_COV_UNR
419		excluded
			Exclude Annotation: VC_COV_UNR
421	1	1
			Exclude Annotation: VC_COV_UNR
430	2	2
			MISSING_ELSE
433	1	1
459	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Total	Covered	Percent
Conditions	59	59	100.00
Logical	59	59	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       60
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (((!sha_en_i)) || clear_digest)
             ------1------    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((((~sha_en_i)) || hash_start_i) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (((~sha_en_i)) || hash_start_i)
                 ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       404
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       404
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       404
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       404
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       404
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       404
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       417
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       430
 EXPRESSION (((!sha_en_i)) || hash_start_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       433
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       433
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       433
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       433
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       433
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       459
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_start_i)))
             -----------1-----------    ----------2----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       459
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       459
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	314	Covered	T13
FifoLoadFromFifo	320	Covered	T13
FifoWait	330	Covered	T13

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	320	Covered	T13
FifoLoadFromFifo->FifoIdle	314	Covered	T13
FifoLoadFromFifo->FifoWait	330	Covered	T13
FifoWait->FifoIdle	314	Covered	T13
FifoWait->FifoLoadFromFifo	345	Covered	T13

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	396	Covered	T13
ShaIdle	398	Covered	T13
ShaUpdateDigest	409	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
ShaCompress->ShaIdle	430	Covered	T13
ShaCompress->ShaUpdateDigest	409	Covered	T13
ShaIdle->ShaCompress	396	Covered	T13
ShaUpdateDigest->ShaCompress	419	Excluded		VC_COV_UNR
ShaUpdateDigest->ShaIdle	421	Covered	T13

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Line No.	Total	Covered	Percent
Branches		64	64	100.00
TERNARY	60	3	3	100.00
TERNARY	283	3	3	100.00
TERNARY	433	2	2	100.00
IF	262	4	4	100.00
IF	278	2	2	100.00
IF	288	2	2	100.00
IF	296	2	2	100.00
IF	309	2	2	100.00
CASE	318	8	8	100.00
IF	356	3	3	100.00
IF	365	2	2	100.00
IF	379	2	2	100.00
CASE	392	6	6	100.00
IF	430	2	2	100.00
IF	183	6	6	100.00
IF	202	2	2	100.00
IF	209	4	4	100.00
IF	222	2	2	100.00
IF	229	5	5	100.00
IF	248	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	(hash_start_i) ? 
-2-:	60	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	(((~sha_en_i) || hash_start_i)) ? 
-2-:	283	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	433	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if (((!sha_en_i) || hash_start_i))
-2-:	264	if (run_hash)
-3-:	265	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	296	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	case (fifo_st_q)
-2-:	320	if (hash_start_i)
-3-:	325	if ((!shaf_rvalid))
-4-:	329	if ((w_index_q == 4'd15))
-5-:	340	if ((msg_feed_complete && one_chunk_done))
-6-:	344	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
FifoIdle	1	-	-	-	-	Covered	T1,T2,T3
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T2,T3
FifoWait	-	-	-	1	-	Covered	T1,T2,T3
FifoWait	-	-	-	0	1	Covered	T1,T2,T3
FifoWait	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	356	if ((!sha_en_i))
-2-:	359	if (hash_start_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	case (sha_st_q)
-2-:	394	if ((fifo_st_q == FifoWait))
-3-:	404	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	408	if (one_chunk_done)
-5-:	417	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
ShaIdle	1	-	-	-	Covered	T1,T2,T3
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T3
ShaCompress	-	0	1	-	Covered	T1,T2,T3
ShaCompress	-	0	0	-	Covered	T1,T2,T3
ShaUpdateDigest	-	-	-	1	Excluded		VC_COV_UNR
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	430	if (((!sha_en_i) || hash_start_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (wipe_secret_i)
-2-:	185	if (((!sha_en_i) || hash_start_i))
-3-:	187	if (((!run_hash) && update_w_from_fifo))
-4-:	191	if (calculate_next_w)
-5-:	194	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T2,T3,T5
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	203	if ((!MultimodeEn))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	209	if (wipe_secret_i)
-2-:	213	if (init_hash)
-3-:	215	if (run_hash)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if (wipe_secret_i)
-2-:	233	if (hash_start_i)
-3-:	237	if (((!sha_en_i) || clear_digest))
-4-:	239	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T2,T3,T5
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3