Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.13	100.00	96.52			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.13	100.00	96.52			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.13	100.00	96.52			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.44	99.44	97.74	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_2	100.00	100.00
u_key_3	100.00	100.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_msg_length_lower	95.83	87.50	100.00			100.00
u_msg_length_upper	95.83	87.50	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		197	197	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	770	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	798	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	833	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
ALWAYS	1052	28	28	100.00
CONT_ASSIGN	1082	1	1	100.00
ALWAYS	1086	1	1	100.00
CONT_ASSIGN	1117	1	1	100.00
CONT_ASSIGN	1119	1	1	100.00
CONT_ASSIGN	1121	1	1	100.00
CONT_ASSIGN	1123	1	1	100.00
CONT_ASSIGN	1124	1	1	100.00
CONT_ASSIGN	1126	1	1	100.00
CONT_ASSIGN	1128	1	1	100.00
CONT_ASSIGN	1130	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1135	1	1	100.00
CONT_ASSIGN	1137	1	1	100.00
CONT_ASSIGN	1138	1	1	100.00
CONT_ASSIGN	1140	1	1	100.00
CONT_ASSIGN	1141	1	1	100.00
CONT_ASSIGN	1142	1	1	100.00
CONT_ASSIGN	1144	1	1	100.00
CONT_ASSIGN	1146	1	1	100.00
CONT_ASSIGN	1148	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1151	1	1	100.00
CONT_ASSIGN	1153	1	1	100.00
CONT_ASSIGN	1155	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1157	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1160	1	1	100.00
CONT_ASSIGN	1162	1	1	100.00
CONT_ASSIGN	1163	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1168	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1174	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	1177	1	1	100.00
CONT_ASSIGN	1178	1	1	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
CONT_ASSIGN	1183	1	1	100.00
CONT_ASSIGN	1184	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1187	1	1	100.00
CONT_ASSIGN	1188	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1191	1	1	100.00
ALWAYS	1195	28	28	100.00
ALWAYS	1227	41	41	100.00
CONT_ASSIGN	1360	0	0
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
418	1	1
433	1	1
449	1	1
465	1	1
471	1	1
485	1	1
491	1	1
506	1	1
522	1	1
538	1	1
554	1	1
560	1	1
575	1	1
591	1	1
672	1	1
686	1	1
693	1	1
707	1	1
714	1	1
728	1	1
735	1	1
749	1	1
756	1	1
770	1	1
777	1	1
791	1	1
798	1	1
812	1	1
819	1	1
833	1	1
840	1	1
854	1	1
1052	1	1
1053	1	1
1054	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1
1070	1	1
1071	1	1
1072	1	1
1073	1	1
1074	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1082	1	1
1086	1	1
1117	1	1
1119	1	1
1121	1	1
1123	1	1
1124	1	1
1126	1	1
1128	1	1
1130	1	1
1131	1	1
1133	1	1
1135	1	1
1137	1	1
1138	1	1
1140	1	1
1141	1	1
1142	1	1
1144	1	1
1146	1	1
1148	1	1
1150	1	1
1151	1	1
1153	1	1
1155	1	1
1156	1	1
1157	1	1
1159	1	1
1160	1	1
1162	1	1
1163	1	1
1165	1	1
1166	1	1
1168	1	1
1169	1	1
1171	1	1
1172	1	1
1174	1	1
1175	1	1
1177	1	1
1178	1	1
1180	1	1
1181	1	1
1183	1	1
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
1202	1	1
1203	1	1
1204	1	1
1205	1	1
1206	1	1
1207	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
1212	1	1
1213	1	1
1214	1	1
1215	1	1
1216	1	1
1217	1	1
1218	1	1
1219	1	1
1220	1	1
1221	1	1
1222	1	1
1227	1	1
1228	1	1
1230	1	1
1231	1	1
1232	1	1
1236	1	1
1237	1	1
1238	1	1
1242	1	1
1243	1	1
1244	1	1
1248	1	1
1252	1	1
1253	1	1
1254	1	1
1255	1	1
1259	1	1
1260	1	1
1264	1	1
1265	1	1
1266	1	1
1270	1	1
1274	1	1
1278	1	1
1282	1	1
1286	1	1
1290	1	1
1294	1	1
1298	1	1
1302	1	1
1306	1	1
1310	1	1
1314	1	1
1318	1	1
1322	1	1
1326	1	1
1330	1	1
1334	1	1
1338	1	1
1342	1	1
1346	1	1
1360		unreachable
1368	1	1
1369	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	287	277	96.52
Logical	287	277	96.52
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T42,T43,T44
1	0	Covered	T56,T57,T58

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T42,T43,T44
0	1	0	Covered	T56,T57,T58
1	0	0	Covered	T42,T43,T44

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T56,T57,T58
0	1	0	Covered	T5,T6,T7
1	0	0	Covered	T5,T6,T7

 LINE       1053
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1054
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1055
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T8

 LINE       1056
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       1057
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CFG_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1058
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1059
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1060
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T8

 LINE       1061
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T14

 LINE       1062
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1063
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1064
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1065
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1066
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1067
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_5_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1068
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_6_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1069
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_7_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1070
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1071
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1072
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1073
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1074
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1075
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1076
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1077
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1078
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1079
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1082
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1082
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1086
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       1086
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
27 (addr_hit[26] & ((|(4'...	Covered	T1,T3,T4
26 (addr_hit[25] & ((|(4'...	Covered	T1,T4,T10
25 (addr_hit[24] & ((|(4'...	Covered	T1,T3,T4
24 (addr_hit[23] & ((|(4'...	Covered	T1,T3,T4
23 (addr_hit[22] & ((|(4'...	Covered	T1,T3,T4
22 (addr_hit[21] & ((|(4'...	Covered	T1,T3,T4
21 (addr_hit[20] & ((|(4'...	Covered	T1,T3,T4
20 (addr_hit[19] & ((|(4'...	Covered	T1,T3,T4
19 (addr_hit[18] & ((|(4'...	Covered	T1,T3,T4
18 (addr_hit[17] & ((|(4'...	Covered	T1,T3,T4
17 (addr_hit[16] & ((|(4'...	Covered	T1,T8,T14
16 (addr_hit[15] & ((|(4'...	Covered	T1,T8,T14
15 (addr_hit[14] & ((|(4'...	Covered	T1,T11,T8
14 (addr_hit[13] & ((|(4'...	Covered	T1,T8,T12
13 (addr_hit[12] & ((|(4'...	Covered	T1,T8,T12
12 (addr_hit[11] & ((|(4'...	Covered	T1,T11,T8
11 (addr_hit[10] & ((|(4'...	Covered	T1,T11,T8
10 (addr_hit[9] & ((|(4'b...	Covered	T1,T8,T14
9 (addr_hit[8] & ((|(4'b...	Covered	T1,T8,T14
8 (addr_hit[7] & ((|(4'b...	Covered	T1,T10,T8
7 (addr_hit[6] & ((|(4'b...	Covered	T1,T3,T4
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T11,T8
5 (addr_hit[4] & ((|(4'b...	Covered	T1,T8,T12
4 (addr_hit[3] & ((|(4'b...	Covered	T1,T2,T8
3 (addr_hit[2] & ((|(4'b...	Covered	T1,T10,T8
2 (addr_hit[1] & ((|(4'b...	Covered	T1,T10,T11
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T10,T11

 LINE       1086
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8
1	1	Covered	T1,T10,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T12

 LINE       1086
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T11,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8
1	1	Covered	T1,T10,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T8,T14

 LINE       1086
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T14

 LINE       1086
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T11,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T11,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T12

 LINE       1086
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T12

 LINE       1086
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T11,T8

 LINE       1086
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T14

 LINE       1086
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T8,T14

 LINE       1086
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1086
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T4,T10

 LINE       1086
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T10
1	1	Covered	T1,T3,T4

 LINE       1117
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1124
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1131
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T10,T8
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T10,T5,T41

 LINE       1138
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T2,T13,T25

 LINE       1141
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       1142
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1151
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1156
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1157
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T8,T14
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T15,T17,T5

 LINE       1160
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1163
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1166
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1169
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1172
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1175
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1178
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1181
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T1,T3,T4

 LINE       1184
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1185
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1186
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1187
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1188
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1189
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1190
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       1191
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		37	37	100.00
TERNARY	1082	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1228	28	28	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1082	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T42,T43,T44
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T56,T57,T58
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1228	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T3,T4
addr_hit[2]	Covered	T1,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T3,T4
addr_hit[5]	Covered	T1,T3,T4
addr_hit[6]	Covered	T1,T3,T4
addr_hit[7]	Covered	T1,T3,T4
addr_hit[8]	Covered	T1,T3,T4
addr_hit[9]	Covered	T1,T3,T4
addr_hit[10]	Covered	T1,T3,T4
addr_hit[11]	Covered	T1,T3,T4
addr_hit[12]	Covered	T1,T3,T4
addr_hit[13]	Covered	T1,T3,T4
addr_hit[14]	Covered	T1,T3,T4
addr_hit[15]	Covered	T1,T3,T4
addr_hit[16]	Covered	T1,T3,T4
addr_hit[17]	Covered	T1,T3,T4
addr_hit[18]	Covered	T1,T3,T4
addr_hit[19]	Covered	T1,T3,T4
addr_hit[20]	Covered	T1,T3,T4
addr_hit[21]	Covered	T1,T3,T4
addr_hit[22]	Covered	T1,T3,T4
addr_hit[23]	Covered	T1,T3,T4
addr_hit[24]	Covered	T1,T3,T4
addr_hit[25]	Covered	T1,T3,T4
addr_hit[26]	Covered	T1,T3,T4
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	383866107	51354033	0	0
reAfterRv	383866107	51354033	0	0
rePulse	383866107	28701465	0	0
wePulse	383866107	22652568	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	51354033	0	0
T1	611639	41478	0	0
T2	974	26	0	0
T3	4691	210	0	0
T4	4755	180	0	0
T8	173106	49900	0	0
T9	114267	32641	0	0
T10	951627	101974	0	0
T11	5064	563	0	0
T12	2770	292	0	0
T13	1493	12	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	51354033	0	0
T1	611639	41478	0	0
T2	974	26	0	0
T3	4691	210	0	0
T4	4755	180	0	0
T8	173106	49900	0	0
T9	114267	32641	0	0
T10	951627	101974	0	0
T11	5064	563	0	0
T12	2770	292	0	0
T13	1493	12	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	28701465	0	0
T1	611639	27591	0	0
T2	974	1	0	0
T3	4691	89	0	0
T4	4755	101	0	0
T8	173106	33307	0	0
T9	114267	21722	0	0
T10	951627	536489	0	0
T11	5064	381	0	0
T12	2770	183	0	0
T13	1493	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	22652568	0	0
T1	611639	13887	0	0
T2	974	25	0	0
T3	4691	121	0	0
T4	4755	79	0	0
T8	173106	16593	0	0
T9	114267	10919	0	0
T10	951627	483256	0	0
T11	5064	182	0	0
T12	2770	109	0	0
T13	1493	11	0	0