Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	85.92	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	99.06	100.00	95.31	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	95.31	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34	99.55	98.55	100.00	100.00	98.47	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	100.00	100.00	100.00		100.00	100.00
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_256	98.67	100.00	100.00		100.00	94.69
u_reg	99.44	99.44	97.74	100.00		100.00	100.00
u_tlul_adapter	97.46	98.54	100.00			98.44	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		115	115	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	122	8	8	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
ALWAYS	169	6	6	100.00
ALWAYS	179	4	4	100.00
ALWAYS	194	6	6	100.00
ALWAYS	207	4	4	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	332	3	3	100.00
ALWAYS	340	6	6	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	520	6	6	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
ALWAYS	573	3	3	100.00
CONT_ASSIGN	579	1	1	100.00
ALWAYS	601	6	6	100.00
ALWAYS	608	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
114	1	1
115	1	1
118	1	1
119	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
			MISSING_ELSE
			MISSING_ELSE
139	8	8
144	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
156	1	1
157	1	1
160	1	1
161	1	1
166	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
			MISSING_ELSE
179	1	1
180	1	1
187	1	1
188	1	1
			MISSING_ELSE
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
			MISSING_ELSE
207	1	1
208	1	1
209	1	1
210	1	1
			MISSING_ELSE
213	1	1
216	1	1
260	1	1
263	1	1
267	1	1
268	1	1
270	1	1
271	1	1
272	1	1
273	1	1
327	1	1
332	1	1
333	1	1
334	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
			MISSING_ELSE
350	1	1
352	1	1
360	1	1
361	1	1
466	1	1
494	1	1
495	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
507	1	1
515	1	1
520	1	1
521	1	1
523	1	1
527	1	1
531	1	1
535	1	1
548	1	1
567	1	1
571	1	1
573	1	1
574	1	1
576	1	1
579	1	1
601	2	2
602	2	2
603	2	2
			MISSING_ELSE
608	2	2
609	2	2
610	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	71	61	85.92
Logical	71	61	85.92
Non-Logical	0	0
Event	0	0

 LINE       156
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       166
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T10,T26,T27
1	1	0	Covered	T10,T26,T27
1	1	1	Covered	T1,T3,T4

 LINE       187
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       213
 EXPRESSION (fifo_empty & ((~fifo_empty_q)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       260
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       263
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T8,T9,T5
1	1	1	Covered	T1,T3,T4

 LINE       272
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       272
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       273
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       280
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       327
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T10,T26,T27
1	1	1	1	Covered	T1,T3,T4

 LINE       344
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Unreachable	T8,T9,T5
1	1	1	Covered	T1,T3,T4

 LINE       367
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       367
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T25

 LINE       494
 EXPRESSION (reg_hash_start & ((~sha_en)))
             -------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       495
 EXPRESSION (reg_hash_start & cfg_block)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       496
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       515
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T27

 LINE       515
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T10,T26,T27
0	0	1	0	Covered	T10,T26,T27
0	1	0	0	Covered	T10,T26,T27
1	0	0	0	Covered	T10,T26,T27

 LINE       567
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T4
1	1	1	0	Covered	T1,T10,T11
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T5,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T13,T25	Yes	T2,T13,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T13,T25	Yes	T2,T13,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_hmac_err_o	Yes	Yes	T10,T26,T27	Yes	T10,T26,T27	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	272	2	2	100.00
TERNARY	273	2	2	100.00
IF	122	4	4	100.00
IF	169	4	4	100.00
IF	179	3	3	100.00
IF	194	4	4	100.00
IF	207	3	3	100.00
IF	340	4	4	100.00
IF	500	2	2	100.00
CASE	521	5	5	100.00
IF	573	2	2	100.00
IF	601	4	4	100.00
IF	608	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	272	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	if ((!rst_ni))
-2-:	124	if (wipe_secret)
-3-:	126	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T17,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	169	if ((!rst_ni))
-2-:	171	if (hash_start)
-3-:	173	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	179	if ((!rst_ni))
-2-:	187	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))
-2-:	196	if (hash_start)
-3-:	198	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	209	if ((!hmac_fifo_wsel))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	342	if (hash_start)
-3-:	344	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	500	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	521	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T10,T26,T27
update_seckey_inprocess	Covered	T10,T26,T27
hash_start_active	Covered	T10,T26,T27
msg_push_not_allowed	Covered	T10,T26,T27
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	573	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	if ((!rst_ni))
-2-:	602	if (reg_hash_process)
-3-:	603	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	608	if ((!rst_ni))
-2-:	609	if (hash_start)
-3-:	610	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	375798048	375729219	0	0
FpvSecCmRegWeOnehotCheck_A	375798048	110	0	0
IntrFifoEmptyOKnown	375798048	375729219	0	0
IntrHmacDoneOKnown	375798048	375729219	0	0
MsgFifoEmptyWhenNoOpAssert	375798048	42423925	0	0
TlOAReadyKnown	375798048	375729219	0	0
TlODValidKnown	375798048	375729219	0	0
ValidHashProcessAssert	375798048	40710	0	0
ValidHmacEnConditionAssert	375798048	10554	0	0
ValidWriteAssert	375798048	23000945	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	375798048	23000945	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	110	0	0
T42	8795	20	0	0
T43	0	20	0	0
T44	0	30	0	0
T45	0	30	0	0
T46	0	10	0	0
T47	151102	0	0	0
T48	101544	0	0	0
T49	1136	0	0	0
T50	50995	0	0	0
T51	11157	0	0	0
T52	30396	0	0	0
T53	411795	0	0	0
T54	80529	0	0	0
T55	46350	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

MsgFifoEmptyWhenNoOpAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	42423925	0	0
T1	611639	13805	0	0
T2	974	917	0	0
T3	4691	1769	0	0
T4	4755	2139	0	0
T8	173106	4548	0	0
T9	114267	2897	0	0
T10	951627	494688	0	0
T11	5064	2117	0	0
T12	2770	1192	0	0
T13	1493	1416	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	40710	0	0
T1	611639	45	0	0
T2	974	0	0	0
T3	4691	4	0	0
T4	4755	4	0	0
T8	173106	43	0	0
T9	114267	30	0	0
T10	951627	742	0	0
T11	5064	11	0	0
T12	2770	6	0	0
T13	1493	0	0	0
T14	0	13	0	0
T15	0	5	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	10554	0	0
T1	611639	20	0	0
T2	974	0	0	0
T3	4691	1	0	0
T4	4755	1	0	0
T8	173106	22	0	0
T9	114267	20	0	0
T10	951627	94	0	0
T11	5064	6	0	0
T12	2770	5	0	0
T13	1493	0	0	0
T14	0	7	0	0
T15	0	4	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		115	115	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	122	8	8	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
ALWAYS	169	6	6	100.00
ALWAYS	179	4	4	100.00
ALWAYS	194	6	6	100.00
ALWAYS	207	4	4	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	332	3	3	100.00
ALWAYS	340	6	6	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	520	6	6	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
ALWAYS	573	3	3	100.00
CONT_ASSIGN	579	1	1	100.00
ALWAYS	601	6	6	100.00
ALWAYS	608	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
114	1	1
115	1	1
118	1	1
119	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
130	1	1
			MISSING_ELSE
			MISSING_ELSE
139	8	8
144	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
156	1	1
157	1	1
160	1	1
161	1	1
166	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
			MISSING_ELSE
179	1	1
180	1	1
187	1	1
188	1	1
			MISSING_ELSE
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
			MISSING_ELSE
207	1	1
208	1	1
209	1	1
210	1	1
			MISSING_ELSE
213	1	1
216	1	1
260	1	1
263	1	1
267	1	1
268	1	1
270	1	1
271	1	1
272	1	1
273	1	1
327	1	1
332	1	1
333	1	1
334	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
			MISSING_ELSE
350	1	1
352	1	1
360	1	1
361	1	1
466	1	1
494	1	1
495	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
507	1	1
515	1	1
520	1	1
521	1	1
523	1	1
527	1	1
531	1	1
535	1	1
548	1	1
567	1	1
571	1	1
573	1	1
574	1	1
576	1	1
579	1	1
601	2	2
602	2	2
603	2	2
			MISSING_ELSE
608	2	2
609	2	2
610	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	64	61	95.31
Logical	64	61	95.31
Non-Logical	0	0
Event	0	0

 LINE       156
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       166
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T10,T26,T27
1	1	0	Covered	T10,T26,T27
1	1	1	Covered	T1,T3,T4

 LINE       187
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       213
 EXPRESSION (fifo_empty & ((~fifo_empty_q)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       260
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Excluded		VC_COV_UNR

 LINE       263
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T8,T9,T5
1	1	1	Covered	T1,T3,T4

 LINE       272
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       272
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       273
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       280
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       327
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T10,T26,T27
1	1	1	1	Covered	T1,T3,T4

 LINE       344
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Unreachable	T8,T9,T5
1	1	1	Covered	T1,T3,T4

 LINE       367
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       367
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T25

 LINE       494
 EXPRESSION (reg_hash_start & ((~sha_en)))
             -------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       495
 EXPRESSION (reg_hash_start & cfg_block)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       496
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T26,T27

 LINE       515
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T27

 LINE       515
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T10,T26,T27
0	0	1	0	Covered	T10,T26,T27
0	1	0	0	Covered	T10,T26,T27
1	0	0	0	Covered	T10,T26,T27

 LINE       567
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T4
1	1	1	0	Covered	T1,T10,T11
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T5,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T13,T25	Yes	T2,T13,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T13,T25	Yes	T2,T13,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_hmac_err_o	Yes	Yes	T10,T26,T27	Yes	T10,T26,T27	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	272	2	2	100.00
TERNARY	273	2	2	100.00
IF	122	4	4	100.00
IF	169	4	4	100.00
IF	179	3	3	100.00
IF	194	4	4	100.00
IF	207	3	3	100.00
IF	340	4	4	100.00
IF	500	2	2	100.00
CASE	521	5	5	100.00
IF	573	2	2	100.00
IF	601	4	4	100.00
IF	608	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	272	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	if ((!rst_ni))
-2-:	124	if (wipe_secret)
-3-:	126	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T17,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	169	if ((!rst_ni))
-2-:	171	if (hash_start)
-3-:	173	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	179	if ((!rst_ni))
-2-:	187	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))
-2-:	196	if (hash_start)
-3-:	198	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	209	if ((!hmac_fifo_wsel))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	342	if (hash_start)
-3-:	344	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	500	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	521	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T10,T26,T27
update_seckey_inprocess	Covered	T10,T26,T27
hash_start_active	Covered	T10,T26,T27
msg_push_not_allowed	Covered	T10,T26,T27
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	573	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	if ((!rst_ni))
-2-:	602	if (reg_hash_process)
-3-:	603	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	608	if ((!rst_ni))
-2-:	609	if (hash_start)
-3-:	610	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	375798048	375729219	0	0
FpvSecCmRegWeOnehotCheck_A	375798048	110	0	0
IntrFifoEmptyOKnown	375798048	375729219	0	0
IntrHmacDoneOKnown	375798048	375729219	0	0
MsgFifoEmptyWhenNoOpAssert	375798048	42423925	0	0
TlOAReadyKnown	375798048	375729219	0	0
TlODValidKnown	375798048	375729219	0	0
ValidHashProcessAssert	375798048	40710	0	0
ValidHmacEnConditionAssert	375798048	10554	0	0
ValidWriteAssert	375798048	23000945	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	375798048	23000945	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	375798048	23000945	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	110	0	0
T42	8795	20	0	0
T43	0	20	0	0
T44	0	30	0	0
T45	0	30	0	0
T46	0	10	0	0
T47	151102	0	0	0
T48	101544	0	0	0
T49	1136	0	0	0
T50	50995	0	0	0
T51	11157	0	0	0
T52	30396	0	0	0
T53	411795	0	0	0
T54	80529	0	0	0
T55	46350	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

MsgFifoEmptyWhenNoOpAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	42423925	0	0
T1	611639	13805	0	0
T2	974	917	0	0
T3	4691	1769	0	0
T4	4755	2139	0	0
T8	173106	4548	0	0
T9	114267	2897	0	0
T10	951627	494688	0	0
T11	5064	2117	0	0
T12	2770	1192	0	0
T13	1493	1416	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	375729219	0	0
T1	611639	611573	0	0
T2	974	917	0	0
T3	4691	4618	0	0
T4	4755	4663	0	0
T8	173106	173025	0	0
T9	114267	114204	0	0
T10	951627	951574	0	0
T11	5064	4977	0	0
T12	2770	2709	0	0
T13	1493	1416	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	40710	0	0
T1	611639	45	0	0
T2	974	0	0	0
T3	4691	4	0	0
T4	4755	4	0	0
T8	173106	43	0	0
T9	114267	30	0	0
T10	951627	742	0	0
T11	5064	11	0	0
T12	2770	6	0	0
T13	1493	0	0	0
T14	0	13	0	0
T15	0	5	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	10554	0	0
T1	611639	20	0	0
T2	974	0	0	0
T3	4691	1	0	0
T4	4755	1	0	0
T8	173106	22	0	0
T9	114267	20	0	0
T10	951627	94	0	0
T11	5064	6	0	0
T12	2770	5	0	0
T13	1493	0	0	0
T14	0	7	0	0
T15	0	4	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	375798048	23000945	0	0
T1	611639	26760	0	0
T2	974	0	0	0
T3	4691	47	0	0
T4	4755	48	0	0
T8	173106	31873	0	0
T9	114267	20912	0	0
T10	951627	331130	0	0
T11	5064	85	0	0
T12	2770	53	0	0
T13	1493	0	0	0
T14	0	5876	0	0
T15	0	3770	0	0