Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	383866107	1863348	0	0
intr_enable_rd_A	383866107	3991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	1863348	0	0
T5	570719	275279	0	0
T6	0	239827	0	0
T7	0	91033	0	0
T16	0	204540	0	0
T20	272004	0	0	0
T33	569039	0	0	0
T34	2674	0	0	0
T35	923766	0	0	0
T36	213775	0	0	0
T37	13039	0	0	0
T38	33761	0	0	0
T39	62790	0	0	0
T40	166659	0	0	0
T59	0	71445	0	0
T60	0	198053	0	0
T61	0	52802	0	0
T62	0	27057	0	0
T63	0	361126	0	0
T64	0	335	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383866107	3991	0	0
T30	72026	0	0	0
T31	131771	0	0	0
T41	733399	20	0	0
T65	0	13	0	0
T66	0	3	0	0
T67	0	55	0	0
T68	0	49	0	0
T69	0	10	0	0
T70	0	54	0	0
T71	0	29	0	0
T72	0	30	0	0
T73	0	41	0	0
T74	4152	0	0	0
T75	2616	0	0	0
T76	453456	0	0	0
T77	4807	0	0	0
T78	258774	0	0	0
T79	17378	0	0	0
T80	395017	0	0	0