Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256	100.00	100.00

---

Module Instance : tb.dut.u_prim_sha2_256

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	100.00		100.00	94.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sha256_logic.u_prim_sha2_256	98.67	100.00	100.00		100.00	94.69

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	39	0	0
ALWAYS	234	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
234	1	1
235	1	1
236	1	1