Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39148082

1

T1

32234

T2

41984

T3

47796

full_word

36618045

1

T1

26889

T2

34198

T3

36686

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75765747	1			T1	59123		T2	76182		T3	84482
auto[TlIntgErrCmd]	123	1			T51	13		T52	3		T53	9
auto[TlIntgErrData]	137	1			T51	9		T52	5		T53	12
auto[TlIntgErrBoth]	120	1			T51	8		T52	2		T53	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30121647

1

T1

24113

T2

30936

T3

42312

auto[1]

45644480

1

T1

35010

T2

45246

T3

42170

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16173406	1			T1	12060		T2	15679		T3	31716
auto[TlIntgErrNone]	partial	auto[1]	22974318	1			T1	20174		T2	26305		T3	16080
auto[TlIntgErrNone]	full_word	auto[0]	13948090	1			T1	12053		T2	15257		T3	10596
auto[TlIntgErrNone]	full_word	auto[1]	22669933	1			T1	14836		T2	18941		T3	26090
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	6		T52	1		T53	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T51	6		T52	2		T53	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T53	1		T144	1		T145	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T51	1		T146	1		-	-
auto[TlIntgErrData]	partial	auto[0]	63	1			T51	5		T53	8		T141	5
auto[TlIntgErrData]	partial	auto[1]	66	1			T51	3		T52	5		T53	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T142	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T53	1		T142	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T51	3		T52	1		T53	3
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T51	5		T52	1		T53	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T147	1		T148	1		T149	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T144	1		T143	3		T150	1