Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	421752891	2239681	0	0
intr_enable_rd_A	421752891	3375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421752891	2239681	0	0
T4	211172	89237	0	0
T5	0	193702	0	0
T6	0	54303	0	0
T15	0	67476	0	0
T16	0	234262	0	0
T17	0	17746	0	0
T55	0	187269	0	0
T56	0	75890	0	0
T57	0	316352	0	0
T58	0	218762	0	0
T59	122095	0	0	0
T60	4628	0	0	0
T61	40206	0	0	0
T62	21909	0	0	0
T63	81693	0	0	0
T64	2685	0	0	0
T65	3074	0	0	0
T66	1008	0	0	0
T67	5729	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421752891	3375	0	0
T7	858820	4	0	0
T8	226883	0	0	0
T9	6049	0	0	0
T10	177563	0	0	0
T11	77463	0	0	0
T12	786434	0	0	0
T13	1374	0	0	0
T14	598449	0	0	0
T27	139143	0	0	0
T31	9084	0	0	0
T54	0	26	0	0
T68	0	53	0	0
T69	0	4	0	0
T70	0	34	0	0
T71	0	42	0	0
T72	0	8	0	0
T73	0	74	0	0
T74	0	9	0	0
T75	0	31	0	0