Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12962947	1			T1	1407		T2	14		T3	67565
all_values[1]	12962947	1			T1	1407		T2	14		T3	67565
all_values[2]	12962947	1			T1	1407		T2	14		T3	67565

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103416

1

T21

5

T10

2

T18

798

auto[1]

38785425

1

T1

4221

T2

42

T3

202695

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27534114

1

T1

3732

T2

25

T3

133208

auto[1]

11354727

1

T1

489

T2

17

T3

69487

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31690	1			T37	60		T95	54		T7	1
all_values[0]	auto[0]	auto[1]	458	1			T37	2		T95	2		T65	2
all_values[0]	auto[1]	auto[0]	12886158	1			T1	1399		T2	7		T3	67371
all_values[0]	auto[1]	auto[1]	44641	1			T1	8		T2	7		T3	194
all_values[1]	auto[0]	auto[0]	24988	1			T21	3		T18	532		T95	17
all_values[1]	auto[0]	auto[1]	17824	1			T21	2		T18	266		T95	49
all_values[1]	auto[1]	auto[0]	6974171	1			T1	926		T2	4		T3	28131
all_values[1]	auto[1]	auto[1]	5945964	1			T1	481		T2	10		T3	39434
all_values[2]	auto[0]	auto[0]	22126	1			T10	2		T95	56		T7	1
all_values[2]	auto[0]	auto[1]	6330	1			T5	5		T32	2311		T96	2
all_values[2]	auto[1]	auto[0]	7594981	1			T1	1407		T2	14		T3	37706
all_values[2]	auto[1]	auto[1]	5339510	1			T3	29859		T7	5812		T4	22188