---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_tlul_adapter.rvalidHighReqFifoEmpty	0	0	367591876	0	0	0
tb.dut.u_tlul_adapter.rvalidHighWhenRspFifoFull	0	0	367591876	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	367591876	367521080	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	367591876	120	0	0
tb.dut.IntrFifoEmptyOKnown	0	0	367591876	367521080	0	0
tb.dut.IntrHmacDoneOKnown	0	0	367591876	367521080	0	0
tb.dut.TlOAReadyKnown	0	0	367591876	367521080	0	0
tb.dut.TlODValidKnown	0	0	367591876	367521080	0	0
tb.dut.ValidHashProcessAssert	0	0	367591876	40786	0	0
tb.dut.ValidHmacEnConditionAssert	0	0	367591876	10186	0	0
tb.dut.ValidWriteAssert	0	0	367591876	22839114	0	0
tb.dut.gen_assert_wmask_bytealign[0].unnamed$$_0	0	0	367591876	22839114	0	0
tb.dut.gen_assert_wmask_bytealign[1].unnamed$$_0	0	0	367591876	22839114	0	0
tb.dut.gen_assert_wmask_bytealign[2].unnamed$$_0	0	0	367591876	22839114	0	0
tb.dut.gen_assert_wmask_bytealign[3].unnamed$$_0	0	0	367591876	22839114	0	0
tb.dut.hmac_csr_assert.TlulOOBAddrErr_A	0	0	393548241	2477146	0	0
tb.dut.hmac_csr_assert.intr_enable_rd_A	0	0	393548241	2020	0	0
tb.dut.intr_hw_fifo_empty.IntrTKind_A	0	0	569	569	0	0
tb.dut.intr_hw_hmac_done.IntrTKind_A	0	0	569	569	0	0
tb.dut.intr_hw_hmac_err.IntrTKind_A	0	0	569	569	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	393548241	87746549	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	393548241	393436358	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	393548241	123642653	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	393548241	393436358	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	734	734	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	393548709	55784433	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	393548241	1789659	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	393548709	42897907	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	393548709	40489638	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	393548241	1227584	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	393548709	87746549	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	393548709	123642653	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	393548709	87746549	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	393548709	123642653	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	393548709	123642653	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	393548709	123642653	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	393548241	1024247	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	393548241	557163	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	734	734	0	0
tb.dut.u_msg_fifo.DataKnown_A	0	0	367591876	55948799	0	0
tb.dut.u_msg_fifo.DepthKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_msg_fifo.RvalidKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_msg_fifo.WreadyKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_msg_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	367591876	55948799	0	0
tb.dut.u_packer.DataIStable_M	0	0	367591876	3286308	0	569
tb.dut.u_packer.DataOStableWhenPending_A	0	0	367591876	4048469	0	569
tb.dut.u_packer.ExFlushValid_M	0	0	367591876	40786	0	0
tb.dut.u_packer.ExcessiveDataStored_A	0	0	367591876	19124	0	0
tb.dut.u_packer.ExcessiveMaskStored_A	0	0	367591876	19124	0	0
tb.dut.u_packer.FlushFollowedByDone_A	0	0	367591876	40786	0	569
tb.dut.u_packer.ValidIDeassertedOnFlush_M	0	0	367591876	78904	0	0
tb.dut.u_packer.ValidOAssertedForStoredDataGTEOutW_A	0	0	367591876	17995810	0	0
tb.dut.u_packer.ValidOPairedWidthReadyI_A	0	0	367591876	4048469	0	0
tb.dut.u_packer.gen_mask_assert.ContiguousOnesMask_M	0	0	367591876	21795617	0	0
tb.dut.u_reg.en2addrHit	0	0	393548241	50133691	0	0
tb.dut.u_reg.reAfterRv	0	0	393548241	50133691	0	0
tb.dut.u_reg.rePulse	0	0	393548241	27869385	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	734	734	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	734	734	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	734	734	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	734	734	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	734	734	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	734	734	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	734	734	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	734	734	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	393548241	87746549	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
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tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	393548241	123642653	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	734	734	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	393548241	29515916	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
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tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	393548241	36061507	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	734	734	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	393548241	55016670	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	734	734	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	393548241	87581146	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	393548241	393436358	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	734	734	0	0
tb.dut.u_reg.u_socket.maxN	0	0	734	734	0	0
tb.dut.u_reg.wePulse	0	0	393548241	22264306	0	0
tb.dut.u_tlul_adapter.AddrOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.DataIntgOptions_A	0	0	569	569	0	0
tb.dut.u_tlul_adapter.ReqOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.SramDwHasByteGranularity_A	0	0	569	569	0	0
tb.dut.u_tlul_adapter.SramDwIsMultipleOfTlulWidth_A	0	0	569	569	0	0
tb.dut.u_tlul_adapter.TlOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.TlOutPayloadKnown_A	0	0	367591876	32750797	0	0
tb.dut.u_tlul_adapter.TlOutPayloadKnown_AKnownEnable	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.WdataOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.WeOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.WmaskOutKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.adapterNoReadOrWrite	0	0	569	569	0	0
tb.dut.u_tlul_adapter.u_err.dataWidthOnly32_A	0	0	569	569	0	0
tb.dut.u_tlul_adapter.u_reqfifo.DataKnown_A	0	0	367591876	32750797	0	0
tb.dut.u_tlul_adapter.u_reqfifo.DepthKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_reqfifo.RvalidKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_reqfifo.WreadyKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	367591876	32750797	0	0
tb.dut.u_tlul_adapter.u_rsp_gen.DataWidthCheck_A	0	0	569	569	0	0
tb.dut.u_tlul_adapter.u_rsp_gen.PayLoadWidthCheck	0	0	569	569	0	0
tb.dut.u_tlul_adapter.u_rspfifo.DepthKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_rspfifo.RvalidKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_rspfifo.WreadyKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_sramreqfifo.DepthKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_sramreqfifo.RvalidKnown_A	0	0	367591876	367521080	0	0
tb.dut.u_tlul_adapter.u_sramreqfifo.WreadyKnown_A	0	0	367591876	367521080	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_packer.DataIStable_M	0	0	367591876	3286308	0	569
tb.dut.u_packer.DataOStableWhenPending_A	0	0	367591876	4048469	0	569
tb.dut.u_packer.FlushFollowedByDone_A	0	0	367591876	40786	0	569

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	EXCLUDE ANNOTATION	SRC
tb.dut.u_tlul_adapter.u_rspfifo.DataKnown_A	0	0	Excluded	[UNSUPPORTED] excluded by fpv
tb.dut.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	Excluded	[UNSUPPORTED] excluded by fpv
tb.dut.u_tlul_adapter.u_sramreqfifo.DataKnown_A	0	0	Excluded	[UNSUPPORTED] excluded by fpv
tb.dut.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	Excluded	[UNSUPPORTED] excluded by fpv

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	393548709	319041	319041	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	393548709	224	224	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	393548709	226	226	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	393548709	151	151	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	393548709	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	393548709	113	113	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	393548709	102	102	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	393548709	7653	7653	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	393548709	1639104	1639104	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	393548709	30066660	30066660	702

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	393548709	319041	319041	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	393548709	224	224	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	393548709	226	226	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	393548709	151	151	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	393548709	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	393548709	113	113	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	393548709	102	102	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	393548709	7653	7653	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	393548709	1639104	1639104	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	393548709	30066660	30066660	702