Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6273571

1

T1

777

T2

2

T3

37511

auto[1]

2398074

1

T1

621

T2

4

T11

145

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439034

1

T1

1391

T2

5

T11

116

auto[1]

6232611

1

T1

7

T2

1

T3

37511

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5646354

1

T1

500

T2

3

T3

37511

auto[1]

3025291

1

T1

898

T2

3

T11

114

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5509942	1			T1	498		T3	34848		T11	191
fifo_depth[1]	425631	1			T1	97		T3	1611		T11	15
fifo_depth[2]	362168	1			T1	115		T3	680		T11	7
fifo_depth[3]	297092	1			T1	107		T3	262		T11	14
fifo_depth[4]	274552	1			T1	93		T3	82		T11	11
fifo_depth[5]	234391	1			T1	88		T3	20		T11	12
fifo_depth[6]	235913	1			T1	92		T3	6		T11	11
fifo_depth[7]	203092	1			T1	87		T2	1		T3	2
fifo_depth[8]	224570	1			T1	80		T2	1		T11	7
fifo_depth[9]	137991	1			T1	54		T2	1		T11	4
fifo_depth[10]	133154	1			T1	42		T11	3		T21	1
fifo_depth[11]	80115	1			T1	22		T21	1		T9	6
fifo_depth[12]	123613	1			T1	14		T2	1		T21	1
fifo_depth[13]	59994	1			T1	6		T2	1		T11	1
fifo_depth[14]	93795	1			T1	3		T11	1		T9	2
fifo_depth[15]	54730	1			T2	1		T9	2		T10	1
fifo_depth[16]	220902	1			T9	2		T10	1		T18	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3161703

1

T1

900

T2

6

T3

2663

auto[1]

5509942

1

T1

498

T3

34848

T11

191

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8450743

1

T1

1398

T2

6

T3

37511

auto[1]

220902

1

T9

2

T10

1

T18

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

224222

1

T1

310

T2

1

T9

7

auto[0]

auto[0]

auto[0]

auto[1]

231212

1

T2

1

T9

4

T22

252

auto[0]

auto[0]

auto[1]

auto[0]

930745

1

T3

2663

T9

4

T10

3

auto[0]

auto[0]

auto[1]

auto[1]

216415

1

T2

1

T9

2

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

401183

1

T1

173

T2

1

T11

25

auto[0]

auto[1]

auto[0]

auto[1]

394564

1

T1

417

T2

2

T11

33

auto[0]

auto[1]

auto[1]

auto[0]

388777

1

T11

6

T21

28

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

374585

1

T11

32

T21

4

T9

3

auto[1]

auto[0]

auto[0]

auto[0]

236436

1

T1

184

T11

20

T21

9

auto[1]

auto[0]

auto[0]

auto[1]

223178

1

T11

28

T21

27

T17

14

auto[1]

auto[0]

auto[1]

auto[0]

3363087

1

T1

1

T3

34848

T11

84

auto[1]

auto[0]

auto[1]

auto[1]

221059

1

T1

5

T11

41

T21

23

auto[1]

auto[1]

auto[0]

auto[0]

364818

1

T1

109

T11

7

T21

3

auto[1]

auto[1]

auto[0]

auto[1]

363421

1

T1

198

T11

3

T17

124

auto[1]

auto[1]

auto[1]

auto[0]

364303

1

T21

6

T17

272

T22

892

auto[1]

auto[1]

auto[1]

auto[1]

373640

1

T1

1

T11

8

T21

2

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

433053

1

T1

494

T2

1

T11

20

auto[0]

auto[0]

auto[0]

auto[1]

421715

1

T2

1

T11

28

T21

27

auto[0]

auto[0]

auto[1]

auto[0]

4268599

1

T1

1

T3

37511

T11

84

auto[0]

auto[0]

auto[1]

auto[1]

410594

1

T1

5

T2

1

T11

41

auto[0]

auto[1]

auto[0]

auto[0]

737251

1

T1

282

T2

1

T11

32

auto[0]

auto[1]

auto[0]

auto[1]

729962

1

T1

615

T2

2

T11

36

auto[0]

auto[1]

auto[1]

auto[0]

724293

1

T11

6

T21

34

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

725276

1

T1

1

T11

40

T21

6

auto[1]

auto[0]

auto[0]

auto[0]

27605

1

T7

547

T65

1836

T66

758

auto[1]

auto[0]

auto[0]

auto[1]

32675

1

T37

14

T7

265

T65

939

auto[1]

auto[0]

auto[1]

auto[0]

25233

1

T10

1

T7

745

T65

1074

auto[1]

auto[0]

auto[1]

auto[1]

26880

1

T9

1

T7

492

T65

448

auto[1]

auto[1]

auto[0]

auto[0]

28750

1

T9

1

T7

444

T66

71

auto[1]

auto[1]

auto[0]

auto[1]

28023

1

T7

3050

T65

54

T66

165

auto[1]

auto[1]

auto[1]

auto[0]

28787

1

T18

2

T37

28

T7

1391

auto[1]

auto[1]

auto[1]

auto[1]

22949

1

T7

981

T65

55

T66

1285

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	236436	1			T1	184		T11	20		T21	9
fifo_depth[0]	auto[0]	auto[0]	auto[1]	223178	1			T11	28		T21	27		T17	14
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3363087	1			T1	1		T3	34848		T11	84
fifo_depth[0]	auto[0]	auto[1]	auto[1]	221059	1			T1	5		T11	41		T21	23
fifo_depth[0]	auto[1]	auto[0]	auto[0]	364818	1			T1	109		T11	7		T21	3
fifo_depth[0]	auto[1]	auto[0]	auto[1]	363421	1			T1	198		T11	3		T17	124
fifo_depth[0]	auto[1]	auto[1]	auto[0]	364303	1			T21	6		T17	272		T22	892
fifo_depth[0]	auto[1]	auto[1]	auto[1]	373640	1			T1	1		T11	8		T21	2
fifo_depth[1]	auto[0]	auto[0]	auto[0]	20223	1			T1	31		T17	22		T22	15
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18373	1			T22	15		T7	251		T64	1
fifo_depth[1]	auto[0]	auto[1]	auto[0]	204979	1			T3	1611		T17	13		T22	5
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18868	1			T17	13		T22	12		T7	199
fifo_depth[1]	auto[1]	auto[0]	auto[0]	41293	1			T1	25		T11	2		T21	3
fifo_depth[1]	auto[1]	auto[0]	auto[1]	40080	1			T1	41		T11	9		T21	4
fifo_depth[1]	auto[1]	auto[1]	auto[0]	40374	1			T11	1		T21	3		T17	23
fifo_depth[1]	auto[1]	auto[1]	auto[1]	41441	1			T11	3		T21	2		T17	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	18707	1			T1	40		T17	31		T22	33
fifo_depth[2]	auto[0]	auto[0]	auto[1]	17238	1			T22	30		T37	1		T7	258
fifo_depth[2]	auto[0]	auto[1]	auto[0]	158235	1			T3	680		T17	49		T22	52
fifo_depth[2]	auto[0]	auto[1]	auto[1]	17529	1			T17	18		T22	14		T7	216
fifo_depth[2]	auto[1]	auto[0]	auto[0]	38107	1			T1	27		T11	1		T21	5
fifo_depth[2]	auto[1]	auto[0]	auto[1]	37574	1			T1	48		T11	4		T21	3
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37023	1			T11	1		T17	52		T22	82
fifo_depth[2]	auto[1]	auto[1]	auto[1]	37755	1			T11	1		T21	2		T17	3
fifo_depth[3]	auto[0]	auto[0]	auto[0]	15336	1			T1	38		T17	22		T22	15
fifo_depth[3]	auto[0]	auto[0]	auto[1]	14394	1			T22	14		T7	288		T64	3
fifo_depth[3]	auto[0]	auto[1]	auto[0]	118719	1			T3	262		T17	12		T22	17
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14415	1			T17	14		T22	9		T7	187
fifo_depth[3]	auto[1]	auto[0]	auto[0]	34146	1			T1	19		T11	3		T21	5
fifo_depth[3]	auto[1]	auto[0]	auto[1]	33433	1			T1	50		T11	7		T21	3
fifo_depth[3]	auto[1]	auto[1]	auto[0]	32885	1			T21	3		T17	42		T22	33
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33764	1			T11	4		T17	1		T22	16
fifo_depth[4]	auto[0]	auto[0]	auto[0]	17241	1			T1	30		T17	22		T22	41
fifo_depth[4]	auto[0]	auto[0]	auto[1]	16059	1			T22	104		T37	1		T7	370
fifo_depth[4]	auto[0]	auto[1]	auto[0]	88683	1			T3	82		T17	28		T22	36
fifo_depth[4]	auto[0]	auto[1]	auto[1]	15143	1			T17	48		T22	25		T7	221
fifo_depth[4]	auto[1]	auto[0]	auto[0]	34515	1			T1	20		T11	2		T21	5
fifo_depth[4]	auto[1]	auto[0]	auto[1]	35209	1			T1	43		T21	1		T17	12
fifo_depth[4]	auto[1]	auto[1]	auto[0]	33942	1			T11	4		T21	6		T17	60
fifo_depth[4]	auto[1]	auto[1]	auto[1]	33760	1			T11	5		T17	1		T22	39
fifo_depth[5]	auto[0]	auto[0]	auto[0]	14099	1			T1	36		T17	14		T22	29
fifo_depth[5]	auto[0]	auto[0]	auto[1]	13118	1			T22	3		T7	347		T64	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	70827	1			T3	20		T9	1		T17	12
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12345	1			T17	10		T22	12		T7	204
fifo_depth[5]	auto[1]	auto[0]	auto[0]	31830	1			T1	13		T11	4		T22	6
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31701	1			T1	39		T11	2		T21	3
fifo_depth[5]	auto[1]	auto[1]	auto[0]	29744	1			T21	3		T17	37		T22	14
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30727	1			T11	6		T17	1		T22	13
fifo_depth[6]	auto[0]	auto[0]	auto[0]	16152	1			T1	31		T17	10		T22	14
fifo_depth[6]	auto[0]	auto[0]	auto[1]	15520	1			T22	52		T37	1		T7	327
fifo_depth[6]	auto[0]	auto[1]	auto[0]	63488	1			T3	6		T17	7		T22	12
fifo_depth[6]	auto[0]	auto[1]	auto[1]	13664	1			T17	4		T22	19		T7	220
fifo_depth[6]	auto[1]	auto[0]	auto[0]	31823	1			T1	16		T11	3		T22	3
fifo_depth[6]	auto[1]	auto[0]	auto[1]	32421	1			T1	45		T11	4		T17	2
fifo_depth[6]	auto[1]	auto[1]	auto[0]	31724	1			T21	2		T17	35		T22	48
fifo_depth[6]	auto[1]	auto[1]	auto[1]	31121	1			T11	4		T17	1		T22	9
fifo_depth[7]	auto[0]	auto[0]	auto[0]	13642	1			T1	28		T10	1		T17	3
fifo_depth[7]	auto[0]	auto[0]	auto[1]	13461	1			T9	1		T22	2		T37	2
fifo_depth[7]	auto[0]	auto[1]	auto[0]	50629	1			T3	2		T17	7		T22	6
fifo_depth[7]	auto[0]	auto[1]	auto[1]	11349	1			T2	1		T17	3		T22	15
fifo_depth[7]	auto[1]	auto[0]	auto[0]	28708	1			T1	22		T11	4		T21	3
fifo_depth[7]	auto[1]	auto[0]	auto[1]	29715	1			T1	37		T11	3		T22	29
fifo_depth[7]	auto[1]	auto[1]	auto[0]	27550	1			T21	1		T17	11		T22	22
fifo_depth[7]	auto[1]	auto[1]	auto[1]	28038	1			T11	3		T9	3		T17	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	18305	1			T1	27		T2	1		T9	4
fifo_depth[8]	auto[0]	auto[0]	auto[1]	20306	1			T22	22		T37	1		T7	317
fifo_depth[8]	auto[0]	auto[1]	auto[0]	44813	1			T17	12		T22	12		T7	597
fifo_depth[8]	auto[0]	auto[1]	auto[1]	17305	1			T17	11		T22	6		T7	361
fifo_depth[8]	auto[1]	auto[0]	auto[0]	30770	1			T1	14		T11	4		T22	1
fifo_depth[8]	auto[1]	auto[0]	auto[1]	31722	1			T1	39		T11	1		T9	2
fifo_depth[8]	auto[1]	auto[1]	auto[0]	32233	1			T21	4		T9	1		T17	14
fifo_depth[8]	auto[1]	auto[1]	auto[1]	29116	1			T11	2		T22	29		T18	8
fifo_depth[9]	auto[0]	auto[0]	auto[0]	10526	1			T1	18		T9	1		T22	2
fifo_depth[9]	auto[0]	auto[0]	auto[1]	9844	1			T22	2		T37	1		T7	223
fifo_depth[9]	auto[0]	auto[1]	auto[0]	28069	1			T17	3		T7	202		T65	36
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9357	1			T22	2		T7	149		T65	236
fifo_depth[9]	auto[1]	auto[0]	auto[0]	20149	1			T1	6		T11	1		T21	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	20503	1			T1	30		T2	1		T11	1
fifo_depth[9]	auto[1]	auto[1]	auto[0]	19993	1			T21	1		T17	1		T22	13
fifo_depth[9]	auto[1]	auto[1]	auto[1]	19550	1			T11	2		T22	1		T18	5
fifo_depth[10]	auto[0]	auto[0]	auto[0]	11755	1			T1	16		T17	1		T22	1
fifo_depth[10]	auto[0]	auto[0]	auto[1]	12997	1			T22	7		T37	2		T7	232
fifo_depth[10]	auto[0]	auto[1]	auto[0]	22021	1			T10	1		T22	1		T7	175
fifo_depth[10]	auto[0]	auto[1]	auto[1]	12765	1			T7	260		T65	215		T66	73
fifo_depth[10]	auto[1]	auto[0]	auto[0]	18553	1			T1	5		T9	1		T18	24
fifo_depth[10]	auto[1]	auto[0]	auto[1]	18023	1			T1	21		T11	1		T9	1
fifo_depth[10]	auto[1]	auto[1]	auto[0]	19645	1			T21	1		T9	1		T10	1
fifo_depth[10]	auto[1]	auto[1]	auto[1]	17395	1			T11	2		T22	1		T18	5
fifo_depth[11]	auto[0]	auto[0]	auto[0]	7396	1			T1	9		T7	107		T65	73
fifo_depth[11]	auto[0]	auto[0]	auto[1]	6870	1			T9	1		T37	1		T7	202
fifo_depth[11]	auto[0]	auto[1]	auto[0]	13528	1			T9	1		T7	117		T16	163
fifo_depth[11]	auto[0]	auto[1]	auto[1]	7462	1			T9	1		T22	1		T7	69
fifo_depth[11]	auto[1]	auto[0]	auto[0]	11887	1			T1	2		T9	2		T18	15
fifo_depth[11]	auto[1]	auto[0]	auto[1]	11427	1			T1	11		T18	33		T95	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	11074	1			T21	1		T9	1		T17	2
fifo_depth[11]	auto[1]	auto[1]	auto[1]	10471	1			T18	5		T95	1		T7	190
fifo_depth[12]	auto[0]	auto[0]	auto[0]	12736	1			T1	5		T22	2		T7	393
fifo_depth[12]	auto[0]	auto[0]	auto[1]	15178	1			T9	1		T22	1		T37	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	16901	1			T9	2		T7	839		T65	134
fifo_depth[12]	auto[0]	auto[1]	auto[1]	14443	1			T7	323		T65	717		T66	64
fifo_depth[12]	auto[1]	auto[0]	auto[0]	17566	1			T1	3		T18	2		T7	824
fifo_depth[12]	auto[1]	auto[0]	auto[1]	15962	1			T1	6		T2	1		T9	1
fifo_depth[12]	auto[1]	auto[1]	auto[0]	16446	1			T21	1		T17	1		T18	26
fifo_depth[12]	auto[1]	auto[1]	auto[1]	14381	1			T18	2		T95	2		T7	422
fifo_depth[13]	auto[0]	auto[0]	auto[0]	6045	1			T1	1		T9	1		T7	104
fifo_depth[13]	auto[0]	auto[0]	auto[1]	5792	1			T2	1		T37	1		T7	271
fifo_depth[13]	auto[0]	auto[1]	auto[0]	8291	1			T7	69		T65	66		T16	27
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6486	1			T10	1		T7	29		T65	156
fifo_depth[13]	auto[1]	auto[0]	auto[0]	10609	1			T1	1		T10	1		T18	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	7693	1			T1	4		T11	1		T9	2
fifo_depth[13]	auto[1]	auto[1]	auto[0]	7731	1			T21	2		T10	1		T18	8
fifo_depth[13]	auto[1]	auto[1]	auto[1]	7347	1			T18	1		T95	1		T7	197
fifo_depth[14]	auto[0]	auto[0]	auto[0]	9330	1			T10	2		T7	334		T65	259
fifo_depth[14]	auto[0]	auto[0]	auto[1]	12929	1			T37	16		T7	482		T65	543
fifo_depth[14]	auto[0]	auto[1]	auto[0]	10281	1			T7	444		T65	201		T16	13
fifo_depth[14]	auto[0]	auto[1]	auto[1]	12242	1			T7	241		T65	530		T66	56
fifo_depth[14]	auto[1]	auto[0]	auto[0]	13092	1			T11	1		T7	725		T29	2
fifo_depth[14]	auto[1]	auto[0]	auto[1]	12835	1			T1	3		T9	2		T7	451
fifo_depth[14]	auto[1]	auto[1]	auto[0]	12411	1			T18	9		T37	63		T7	673
fifo_depth[14]	auto[1]	auto[1]	auto[1]	10675	1			T7	548		T65	114		T66	923
fifo_depth[15]	auto[0]	auto[0]	auto[0]	5124	1			T9	1		T7	61		T65	61
fifo_depth[15]	auto[0]	auto[0]	auto[1]	6458	1			T9	1		T7	365		T65	500
fifo_depth[15]	auto[0]	auto[1]	auto[0]	6048	1			T10	1		T7	102		T65	66
fifo_depth[15]	auto[0]	auto[1]	auto[1]	6162	1			T7	19		T65	102		T66	50
fifo_depth[15]	auto[1]	auto[0]	auto[0]	9385	1			T2	1		T7	668		T66	5
fifo_depth[15]	auto[1]	auto[0]	auto[1]	8243	1			T18	1		T7	356		T65	108
fifo_depth[15]	auto[1]	auto[1]	auto[0]	7215	1			T37	42		T7	310		T65	77
fifo_depth[15]	auto[1]	auto[1]	auto[1]	6095	1			T7	273		T65	97		T66	626
fifo_depth[16]	auto[0]	auto[0]	auto[0]	27605	1			T7	547		T65	1836		T66	758
fifo_depth[16]	auto[0]	auto[0]	auto[1]	32675	1			T37	14		T7	265		T65	939
fifo_depth[16]	auto[0]	auto[1]	auto[0]	25233	1			T10	1		T7	745		T65	1074
fifo_depth[16]	auto[0]	auto[1]	auto[1]	26880	1			T9	1		T7	492		T65	448
fifo_depth[16]	auto[1]	auto[0]	auto[0]	28750	1			T9	1		T7	444		T66	71
fifo_depth[16]	auto[1]	auto[0]	auto[1]	28023	1			T7	3050		T65	54		T66	165
fifo_depth[16]	auto[1]	auto[1]	auto[0]	28787	1			T18	2		T37	28		T7	1391
fifo_depth[16]	auto[1]	auto[1]	auto[1]	22949	1			T7	981		T65	55		T66	1285