Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12962947	1			T1	1407		T2	14		T3	67565
all_pins[1]	12962947	1			T1	1407		T2	14		T3	67565
all_pins[2]	12962947	1			T1	1407		T2	14		T3	67565

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	27496626	1			T1	3719		T2	25		T3	133126
values[0x1]	11392215	1			T1	502		T2	17		T3	69569
transitions[0x0=>0x1]	9879339	1			T1	498		T2	10		T3	58586
transitions[0x1=>0x0]	9879355	1			T1	498		T2	10		T3	58586

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12917356	1			T1	1399		T2	7		T3	67371
all_pins[0]	values[0x1]	45591	1			T1	8		T2	7		T3	194
all_pins[0]	transitions[0x0=>0x1]	45528	1			T1	8		T2	7		T3	194
all_pins[0]	transitions[0x1=>0x0]	5339463	1			T3	29859		T7	5812		T4	22188
all_pins[1]	values[0x0]	6955833	1			T1	913		T2	4		T3	28049
all_pins[1]	values[0x1]	6007114	1			T1	494		T2	10		T3	39516
all_pins[1]	transitions[0x0=>0x1]	5971349	1			T1	490		T2	3		T3	39372
all_pins[1]	transitions[0x1=>0x0]	9826	1			T1	4		T3	50		T11	8
all_pins[2]	values[0x0]	7623437	1			T1	1407		T2	14		T3	37706
all_pins[2]	values[0x1]	5339510	1			T3	29859		T7	5812		T4	22188
all_pins[2]	transitions[0x0=>0x1]	3862462	1			T3	19020		T7	4004		T4	18297
all_pins[2]	transitions[0x1=>0x0]	4530066	1			T1	494		T2	10		T3	28677