Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 889 1 T5 17 T19 10 T55 17
all_values[1] 889 1 T5 17 T19 10 T55 17
all_values[2] 889 1 T5 17 T19 10 T55 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1380 1 T5 21 T19 12 T55 22
auto[1] 1287 1 T5 30 T19 18 T55 29


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 965 1 T5 18 T19 12 T55 23
auto[1] 1702 1 T5 33 T19 18 T55 28


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1505 1 T5 27 T19 16 T55 30
auto[1] 1162 1 T5 24 T19 14 T55 21


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 167 1 T5 3 T55 2 T113 3
all_values[0] auto[0] auto[0] auto[1] 92 1 T5 2 T19 1 T113 2
all_values[0] auto[0] auto[1] auto[0] 140 1 T5 4 T55 6 T69 1
all_values[0] auto[0] auto[1] auto[1] 92 1 T5 1 T19 3 T55 2
all_values[0] auto[1] auto[0] auto[1] 217 1 T5 2 T19 5 T55 4
all_values[0] auto[1] auto[1] auto[1] 181 1 T5 5 T19 1 T55 3
all_values[1] auto[0] auto[0] auto[0] 173 1 T5 3 T19 4 T55 4
all_values[1] auto[0] auto[0] auto[1] 91 1 T55 3 T113 2 T38 1
all_values[1] auto[0] auto[1] auto[0] 161 1 T5 2 T19 4 T55 2
all_values[1] auto[0] auto[1] auto[1] 84 1 T5 4 T55 1 T69 1
all_values[1] auto[1] auto[0] auto[1] 189 1 T5 4 T55 3 T69 1
all_values[1] auto[1] auto[1] auto[1] 191 1 T5 4 T19 2 T55 4
all_values[2] auto[0] auto[0] auto[0] 163 1 T5 3 T55 2 T69 1
all_values[2] auto[0] auto[0] auto[1] 89 1 T5 1 T69 1 T113 1
all_values[2] auto[0] auto[1] auto[0] 161 1 T5 3 T19 4 T55 7
all_values[2] auto[0] auto[1] auto[1] 92 1 T5 1 T55 1 T70 1
all_values[2] auto[1] auto[0] auto[1] 199 1 T5 3 T19 2 T55 4
all_values[2] auto[1] auto[1] auto[1] 185 1 T5 6 T19 4 T55 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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