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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 98.36 96.63 100.00 90.62 95.83 99.49 99.45


Total test records in report: 734
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T537 /workspace/coverage/default/11.hmac_alert_test.1682669934 Feb 28 04:43:20 PM PST 24 Feb 28 04:43:21 PM PST 24 23682281 ps
T538 /workspace/coverage/default/20.hmac_alert_test.4250470056 Feb 28 04:43:48 PM PST 24 Feb 28 04:43:49 PM PST 24 35513733 ps
T539 /workspace/coverage/default/30.hmac_long_msg.3176119666 Feb 28 04:44:09 PM PST 24 Feb 28 04:44:13 PM PST 24 208238171 ps
T540 /workspace/coverage/default/1.hmac_back_pressure.749854816 Feb 28 04:42:42 PM PST 24 Feb 28 04:43:08 PM PST 24 3180062978 ps
T541 /workspace/coverage/default/25.hmac_back_pressure.1415556109 Feb 28 04:43:58 PM PST 24 Feb 28 04:44:07 PM PST 24 995682791 ps
T542 /workspace/coverage/default/39.hmac_smoke.800113840 Feb 28 04:44:39 PM PST 24 Feb 28 04:44:42 PM PST 24 1307887908 ps
T543 /workspace/coverage/default/24.hmac_datapath_stress.1247672026 Feb 28 04:43:54 PM PST 24 Feb 28 04:44:01 PM PST 24 144944717 ps
T544 /workspace/coverage/default/14.hmac_smoke.4078668475 Feb 28 04:43:27 PM PST 24 Feb 28 04:43:30 PM PST 24 248134525 ps
T545 /workspace/coverage/default/38.hmac_test_sha_vectors.2908691289 Feb 28 04:44:37 PM PST 24 Feb 28 04:52:03 PM PST 24 139342082637 ps
T546 /workspace/coverage/default/8.hmac_datapath_stress.3891848928 Feb 28 04:43:02 PM PST 24 Feb 28 04:43:10 PM PST 24 149421510 ps
T547 /workspace/coverage/default/42.hmac_burst_wr.1448656899 Feb 28 04:44:43 PM PST 24 Feb 28 04:45:43 PM PST 24 2420727440 ps
T548 /workspace/coverage/default/0.hmac_wipe_secret.2873080108 Feb 28 04:42:38 PM PST 24 Feb 28 04:42:55 PM PST 24 326345146 ps
T549 /workspace/coverage/default/16.hmac_back_pressure.2833313080 Feb 28 04:43:31 PM PST 24 Feb 28 04:44:02 PM PST 24 1323646043 ps
T550 /workspace/coverage/default/14.hmac_stress_all.1869514689 Feb 28 04:43:32 PM PST 24 Feb 28 04:46:53 PM PST 24 62796283951 ps
T551 /workspace/coverage/default/43.hmac_burst_wr.2623352135 Feb 28 04:44:50 PM PST 24 Feb 28 04:46:04 PM PST 24 6561660619 ps
T552 /workspace/coverage/default/18.hmac_wipe_secret.701004899 Feb 28 04:43:45 PM PST 24 Feb 28 04:44:58 PM PST 24 3829894790 ps
T553 /workspace/coverage/default/48.hmac_long_msg.1578998897 Feb 28 04:45:04 PM PST 24 Feb 28 04:45:42 PM PST 24 4205755872 ps
T124 /workspace/coverage/default/19.hmac_back_pressure.3961636190 Feb 28 04:43:43 PM PST 24 Feb 28 04:44:30 PM PST 24 5498718020 ps
T554 /workspace/coverage/default/49.hmac_alert_test.2012404003 Feb 28 04:45:15 PM PST 24 Feb 28 04:45:15 PM PST 24 53535717 ps
T555 /workspace/coverage/default/31.hmac_test_hmac_vectors.1290898860 Feb 28 04:44:10 PM PST 24 Feb 28 04:44:11 PM PST 24 134632716 ps
T556 /workspace/coverage/default/6.hmac_test_hmac_vectors.2598909315 Feb 28 04:42:59 PM PST 24 Feb 28 04:43:00 PM PST 24 62008117 ps
T557 /workspace/coverage/default/17.hmac_back_pressure.4055261583 Feb 28 04:43:32 PM PST 24 Feb 28 04:43:40 PM PST 24 250161392 ps
T558 /workspace/coverage/default/2.hmac_stress_all.2572862378 Feb 28 04:42:45 PM PST 24 Feb 28 05:00:52 PM PST 24 255037965242 ps
T559 /workspace/coverage/default/12.hmac_alert_test.3617036662 Feb 28 04:43:24 PM PST 24 Feb 28 04:43:25 PM PST 24 41775974 ps
T560 /workspace/coverage/default/16.hmac_error.2287966117 Feb 28 04:43:33 PM PST 24 Feb 28 04:44:30 PM PST 24 3394018897 ps
T561 /workspace/coverage/default/8.hmac_test_hmac_vectors.3913285077 Feb 28 04:43:06 PM PST 24 Feb 28 04:43:08 PM PST 24 119030440 ps
T562 /workspace/coverage/default/10.hmac_burst_wr.551005991 Feb 28 04:43:19 PM PST 24 Feb 28 04:43:53 PM PST 24 679292527 ps
T563 /workspace/coverage/default/38.hmac_alert_test.3300484298 Feb 28 04:44:34 PM PST 24 Feb 28 04:44:35 PM PST 24 37488028 ps
T564 /workspace/coverage/default/12.hmac_smoke.3559615174 Feb 28 04:43:21 PM PST 24 Feb 28 04:43:25 PM PST 24 316031854 ps
T565 /workspace/coverage/default/7.hmac_smoke.3641516206 Feb 28 04:43:00 PM PST 24 Feb 28 04:43:04 PM PST 24 287900990 ps
T566 /workspace/coverage/default/39.hmac_error.176445194 Feb 28 04:44:39 PM PST 24 Feb 28 04:47:10 PM PST 24 2660725386 ps
T567 /workspace/coverage/default/35.hmac_error.1242207416 Feb 28 04:44:26 PM PST 24 Feb 28 04:46:08 PM PST 24 9739973714 ps
T568 /workspace/coverage/default/17.hmac_error.36302688 Feb 28 04:43:37 PM PST 24 Feb 28 04:46:06 PM PST 24 44871243651 ps
T569 /workspace/coverage/default/2.hmac_test_sha_vectors.2553666898 Feb 28 04:42:44 PM PST 24 Feb 28 04:49:50 PM PST 24 8812581196 ps
T570 /workspace/coverage/default/13.hmac_long_msg.2374751233 Feb 28 04:43:23 PM PST 24 Feb 28 04:43:49 PM PST 24 1006197513 ps
T571 /workspace/coverage/default/42.hmac_test_sha_vectors.2253780230 Feb 28 04:44:46 PM PST 24 Feb 28 04:53:01 PM PST 24 105946528583 ps
T572 /workspace/coverage/default/25.hmac_alert_test.2076521669 Feb 28 04:43:56 PM PST 24 Feb 28 04:43:56 PM PST 24 10698958 ps
T573 /workspace/coverage/default/18.hmac_error.116129236 Feb 28 04:43:41 PM PST 24 Feb 28 04:45:20 PM PST 24 5867385285 ps
T574 /workspace/coverage/default/1.hmac_test_hmac_vectors.839491890 Feb 28 04:42:40 PM PST 24 Feb 28 04:42:42 PM PST 24 44932583 ps
T575 /workspace/coverage/default/4.hmac_datapath_stress.3894799419 Feb 28 04:42:54 PM PST 24 Feb 28 04:43:31 PM PST 24 3100440923 ps
T576 /workspace/coverage/default/19.hmac_error.2515601411 Feb 28 04:43:46 PM PST 24 Feb 28 04:44:46 PM PST 24 1616911787 ps
T577 /workspace/coverage/default/8.hmac_back_pressure.1952721887 Feb 28 04:43:10 PM PST 24 Feb 28 04:43:34 PM PST 24 4250221754 ps
T578 /workspace/coverage/default/47.hmac_back_pressure.281762720 Feb 28 04:45:21 PM PST 24 Feb 28 04:46:04 PM PST 24 3348980981 ps
T579 /workspace/coverage/default/0.hmac_back_pressure.790029499 Feb 28 04:42:38 PM PST 24 Feb 28 04:42:56 PM PST 24 1194412130 ps
T580 /workspace/coverage/default/20.hmac_error.472132032 Feb 28 04:43:52 PM PST 24 Feb 28 04:44:37 PM PST 24 7823094169 ps
T581 /workspace/coverage/default/5.hmac_test_hmac_vectors.1121463663 Feb 28 04:42:55 PM PST 24 Feb 28 04:42:57 PM PST 24 468587978 ps
T582 /workspace/coverage/default/43.hmac_smoke.2756808935 Feb 28 04:44:45 PM PST 24 Feb 28 04:44:47 PM PST 24 129839313 ps
T583 /workspace/coverage/default/1.hmac_error.3673803611 Feb 28 04:42:45 PM PST 24 Feb 28 04:44:29 PM PST 24 7767972102 ps
T584 /workspace/coverage/default/36.hmac_error.2476547873 Feb 28 04:44:27 PM PST 24 Feb 28 04:45:06 PM PST 24 2352755360 ps
T585 /workspace/coverage/default/33.hmac_burst_wr.3083505942 Feb 28 04:44:12 PM PST 24 Feb 28 04:44:35 PM PST 24 12362245844 ps
T122 /workspace/coverage/default/19.hmac_stress_all.864554758 Feb 28 04:43:45 PM PST 24 Feb 28 05:06:41 PM PST 24 57892091945 ps
T586 /workspace/coverage/default/1.hmac_test_sha_vectors.942790507 Feb 28 04:42:46 PM PST 24 Feb 28 04:49:36 PM PST 24 48772024530 ps
T587 /workspace/coverage/default/3.hmac_test_hmac_vectors.3515481967 Feb 28 04:42:47 PM PST 24 Feb 28 04:42:48 PM PST 24 349033017 ps
T27 /workspace/coverage/default/4.hmac_sec_cm.2938958556 Feb 28 04:42:52 PM PST 24 Feb 28 04:42:53 PM PST 24 378682703 ps
T588 /workspace/coverage/default/48.hmac_test_hmac_vectors.3523097317 Feb 28 04:45:07 PM PST 24 Feb 28 04:45:08 PM PST 24 175343565 ps
T589 /workspace/coverage/default/47.hmac_long_msg.2083274272 Feb 28 04:45:21 PM PST 24 Feb 28 04:45:38 PM PST 24 4323561444 ps
T590 /workspace/coverage/default/20.hmac_stress_all.2656510645 Feb 28 04:43:46 PM PST 24 Feb 28 04:49:15 PM PST 24 12400474647 ps
T591 /workspace/coverage/default/9.hmac_long_msg.381957055 Feb 28 04:43:07 PM PST 24 Feb 28 04:43:20 PM PST 24 3395147643 ps
T592 /workspace/coverage/default/24.hmac_test_hmac_vectors.1384827292 Feb 28 04:43:54 PM PST 24 Feb 28 04:43:56 PM PST 24 31377745 ps
T593 /workspace/coverage/default/7.hmac_test_hmac_vectors.2871827896 Feb 28 04:43:01 PM PST 24 Feb 28 04:43:02 PM PST 24 31355333 ps
T594 /workspace/coverage/default/31.hmac_smoke.633102989 Feb 28 04:44:08 PM PST 24 Feb 28 04:44:10 PM PST 24 581538905 ps
T595 /workspace/coverage/default/3.hmac_long_msg.3214251778 Feb 28 04:42:44 PM PST 24 Feb 28 04:44:09 PM PST 24 26360290966 ps
T596 /workspace/coverage/default/16.hmac_long_msg.2999655291 Feb 28 04:43:35 PM PST 24 Feb 28 04:44:36 PM PST 24 4460268954 ps
T597 /workspace/coverage/default/35.hmac_test_hmac_vectors.4178252397 Feb 28 04:44:31 PM PST 24 Feb 28 04:44:33 PM PST 24 96725257 ps
T598 /workspace/coverage/default/43.hmac_test_sha_vectors.1194687181 Feb 28 04:44:52 PM PST 24 Feb 28 04:51:30 PM PST 24 51625471890 ps
T599 /workspace/coverage/default/21.hmac_test_sha_vectors.3069465348 Feb 28 04:43:52 PM PST 24 Feb 28 04:51:51 PM PST 24 42845189377 ps
T600 /workspace/coverage/default/38.hmac_error.2559510801 Feb 28 04:44:37 PM PST 24 Feb 28 04:47:21 PM PST 24 13274359858 ps
T601 /workspace/coverage/default/7.hmac_test_sha_vectors.191153249 Feb 28 04:43:08 PM PST 24 Feb 28 04:49:34 PM PST 24 16135363862 ps
T602 /workspace/coverage/default/32.hmac_error.2243185451 Feb 28 04:44:16 PM PST 24 Feb 28 04:46:11 PM PST 24 9327767589 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.501057904 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:14 PM PST 24 133380898 ps
T604 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1866491701 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:15 PM PST 24 15182751 ps
T56 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3715621390 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 18824315 ps
T57 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3859476457 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:16 PM PST 24 98174533 ps
T58 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.147012012 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:23 PM PST 24 72502862 ps
T605 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2940008820 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:17 PM PST 24 79298988 ps
T606 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1402050165 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 16624165 ps
T78 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1380570335 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 51055600 ps
T52 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2481972673 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:26 PM PST 24 108076324 ps
T607 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3609945951 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:07 PM PST 24 79493557 ps
T608 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4055267944 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:15 PM PST 24 44599976 ps
T609 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3199402245 Feb 28 04:17:35 PM PST 24 Feb 28 04:17:37 PM PST 24 30930544 ps
T610 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3286663544 Feb 28 04:16:56 PM PST 24 Feb 28 04:16:57 PM PST 24 47569922 ps
T611 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2934392306 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:20 PM PST 24 12175514 ps
T53 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1901579839 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:20 PM PST 24 120465470 ps
T612 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3796574001 Feb 28 04:17:07 PM PST 24 Feb 28 04:17:07 PM PST 24 14371513 ps
T79 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2769968739 Feb 28 04:16:58 PM PST 24 Feb 28 04:16:59 PM PST 24 12996161 ps
T613 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3684841464 Feb 28 04:17:09 PM PST 24 Feb 28 04:17:12 PM PST 24 91325295 ps
T614 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3543753420 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 16882107 ps
T615 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4186041710 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:19 PM PST 24 33720994 ps
T616 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2003235435 Feb 28 04:16:58 PM PST 24 Feb 28 04:17:02 PM PST 24 162066095 ps
T80 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3704006990 Feb 28 04:17:11 PM PST 24 Feb 28 04:17:12 PM PST 24 32417842 ps
T617 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4228429586 Feb 28 04:18:01 PM PST 24 Feb 28 04:18:03 PM PST 24 68790174 ps
T81 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3706906450 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:23 PM PST 24 14378232 ps
T618 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1766577323 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:18 PM PST 24 14157539 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3582787288 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:06 PM PST 24 37624932 ps
T82 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.677320441 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:18 PM PST 24 15828056 ps
T620 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1805091136 Feb 28 04:17:09 PM PST 24 Feb 28 04:17:10 PM PST 24 173861928 ps
T54 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4148204498 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:00 PM PST 24 207130053 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1841854384 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:01 PM PST 24 108396011 ps
T59 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3103648974 Feb 28 04:18:09 PM PST 24 Feb 28 04:18:11 PM PST 24 115903428 ps
T622 /workspace/coverage/cover_reg_top/28.hmac_intr_test.435903514 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 29938106 ps
T623 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3002218179 Feb 28 04:16:58 PM PST 24 Feb 28 04:17:00 PM PST 24 122540675 ps
T624 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3859934074 Feb 28 04:17:30 PM PST 24 Feb 28 04:17:31 PM PST 24 55380020 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2895126627 Feb 28 04:17:07 PM PST 24 Feb 28 04:17:08 PM PST 24 24554479 ps
T131 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1290368492 Feb 28 04:16:56 PM PST 24 Feb 28 04:16:58 PM PST 24 44658177 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2038552108 Feb 28 04:18:02 PM PST 24 Feb 28 04:18:04 PM PST 24 129185593 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3656065663 Feb 28 04:17:23 PM PST 24 Feb 28 04:17:24 PM PST 24 57532527 ps
T628 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3718440206 Feb 28 04:17:33 PM PST 24 Feb 28 04:17:34 PM PST 24 44695042 ps
T629 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1805503792 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:17 PM PST 24 39900981 ps
T630 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4065394234 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:16 PM PST 24 90923225 ps
T631 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1343058492 Feb 28 04:19:03 PM PST 24 Feb 28 04:19:04 PM PST 24 53180242 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2153455007 Feb 28 04:17:24 PM PST 24 Feb 28 04:17:25 PM PST 24 50263043 ps
T633 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1535470831 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:14 PM PST 24 22246046 ps
T634 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1925506054 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:15 PM PST 24 186611912 ps
T83 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1024847057 Feb 28 04:16:55 PM PST 24 Feb 28 04:16:56 PM PST 24 27862720 ps
T138 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2556939244 Feb 28 04:16:58 PM PST 24 Feb 28 04:17:00 PM PST 24 408212776 ps
T635 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3589285850 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:18 PM PST 24 22793432 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2731681255 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:14 PM PST 24 34670297 ps
T637 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1243298675 Feb 28 04:17:06 PM PST 24 Feb 28 04:17:09 PM PST 24 57711592 ps
T638 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2126170649 Feb 28 04:17:23 PM PST 24 Feb 28 04:17:23 PM PST 24 18328589 ps
T639 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.860137727 Feb 28 04:17:08 PM PST 24 Feb 28 04:17:11 PM PST 24 848861261 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.509476713 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:22 PM PST 24 16383683 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1896833244 Feb 28 04:16:57 PM PST 24 Feb 28 04:16:59 PM PST 24 51824642 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.991312485 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:25 PM PST 24 135740135 ps
T643 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1169124752 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:16 PM PST 24 29538841 ps
T644 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1583919252 Feb 28 04:17:38 PM PST 24 Feb 28 04:17:40 PM PST 24 189540514 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.496505755 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:23 PM PST 24 123288222 ps
T84 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2570519695 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:23 PM PST 24 16283165 ps
T133 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2902529403 Feb 28 04:18:15 PM PST 24 Feb 28 04:18:18 PM PST 24 2128696917 ps
T136 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2065293256 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:03 PM PST 24 412134059 ps
T646 /workspace/coverage/cover_reg_top/22.hmac_intr_test.548932158 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 14982163 ps
T85 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2085052526 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:06 PM PST 24 46216072 ps
T647 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1673911853 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:18 PM PST 24 152927817 ps
T648 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1055638351 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:17 PM PST 24 19513206 ps
T649 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3918270521 Feb 28 04:17:48 PM PST 24 Feb 28 04:17:52 PM PST 24 130498124 ps
T132 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1343016825 Feb 28 04:18:30 PM PST 24 Feb 28 04:18:32 PM PST 24 434053486 ps
T650 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.797991585 Feb 28 04:17:17 PM PST 24 Feb 28 04:17:18 PM PST 24 28876241 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3725453538 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:14 PM PST 24 51928465 ps
T652 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3745236339 Feb 28 04:17:11 PM PST 24 Feb 28 04:17:14 PM PST 24 324777122 ps
T653 /workspace/coverage/cover_reg_top/6.hmac_intr_test.325434744 Feb 28 04:17:09 PM PST 24 Feb 28 04:17:10 PM PST 24 12719380 ps
T654 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3766807090 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 95170898 ps
T655 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1187511283 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:19 PM PST 24 16713096 ps
T656 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1340967758 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:15 PM PST 24 153968226 ps
T86 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3733201186 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:07 PM PST 24 212385261 ps
T657 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3006947132 Feb 28 04:17:12 PM PST 24 Feb 28 04:17:15 PM PST 24 481673619 ps
T87 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.356527803 Feb 28 04:17:53 PM PST 24 Feb 28 04:17:54 PM PST 24 14119265 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2569361605 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:19 PM PST 24 64344105 ps
T659 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1147204727 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:02 PM PST 24 224262745 ps
T660 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4145517011 Feb 28 04:17:07 PM PST 24 Feb 28 04:17:09 PM PST 24 38473093 ps
T661 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.239045257 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:21 PM PST 24 117246694 ps
T662 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3953955801 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:02 PM PST 24 71332358 ps
T663 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.672566061 Feb 28 04:17:06 PM PST 24 Feb 28 04:17:07 PM PST 24 25417457 ps
T664 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2300680507 Feb 28 04:17:09 PM PST 24 Feb 28 04:31:53 PM PST 24 387538819928 ps
T665 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2699850275 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:20 PM PST 24 64787444 ps
T666 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2540801796 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:19 PM PST 24 20120066 ps
T667 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1875863380 Feb 28 04:17:06 PM PST 24 Feb 28 04:17:16 PM PST 24 2486338462 ps
T668 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3458352238 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 10801345 ps
T669 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1312535990 Feb 28 04:17:19 PM PST 24 Feb 28 04:17:21 PM PST 24 45738002 ps
T670 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3372048706 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:07 PM PST 24 30923022 ps
T671 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1149258423 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:18 PM PST 24 361737172 ps
T672 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1138416746 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:16 PM PST 24 89439748 ps
T673 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1452833908 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 43491783 ps
T674 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1712534976 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 59786426 ps
T675 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2725462933 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:17 PM PST 24 727706018 ps
T676 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4000685096 Feb 28 04:17:32 PM PST 24 Feb 28 04:17:34 PM PST 24 421538458 ps
T677 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2133469950 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:05 PM PST 24 43910850 ps
T678 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1504044019 Feb 28 04:17:23 PM PST 24 Feb 28 04:17:24 PM PST 24 68997355 ps
T679 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2581047386 Feb 28 04:17:24 PM PST 24 Feb 28 04:17:25 PM PST 24 33148364 ps
T88 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1646715097 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:00 PM PST 24 65507664 ps
T680 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.781927778 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:22 PM PST 24 219592944 ps
T681 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.120641842 Feb 28 04:17:17 PM PST 24 Feb 28 04:20:40 PM PST 24 101603526710 ps
T682 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.256485133 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:08 PM PST 24 659465204 ps
T683 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.331473041 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:20 PM PST 24 661710043 ps
T684 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2449959730 Feb 28 04:17:10 PM PST 24 Feb 28 04:17:12 PM PST 24 54671753 ps
T685 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2354470951 Feb 28 04:17:46 PM PST 24 Feb 28 04:17:48 PM PST 24 23708100 ps
T135 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.204327655 Feb 28 04:17:32 PM PST 24 Feb 28 04:17:34 PM PST 24 183006834 ps
T686 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3170909404 Feb 28 04:17:45 PM PST 24 Feb 28 04:17:45 PM PST 24 14617160 ps
T687 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2896642763 Feb 28 04:17:10 PM PST 24 Feb 28 04:17:11 PM PST 24 34045786 ps
T688 /workspace/coverage/cover_reg_top/17.hmac_intr_test.869150837 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 14669460 ps
T689 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1672513982 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:01 PM PST 24 72862850 ps
T690 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2517417914 Feb 28 04:17:08 PM PST 24 Feb 28 04:17:09 PM PST 24 14853556 ps
T691 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1842200738 Feb 28 04:17:31 PM PST 24 Feb 28 04:17:32 PM PST 24 42544499 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.109827589 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:01 PM PST 24 23118156 ps
T93 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1497706389 Feb 28 04:16:56 PM PST 24 Feb 28 04:16:59 PM PST 24 561583970 ps
T692 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4083170810 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:18 PM PST 24 76915559 ps
T693 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2573799620 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:20 PM PST 24 130075227 ps
T694 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1039761394 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:19 PM PST 24 15720797 ps
T695 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4279588567 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:01 PM PST 24 24547919 ps
T696 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3040797048 Feb 28 04:17:29 PM PST 24 Feb 28 04:17:32 PM PST 24 89254029 ps
T697 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2640496821 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:15 PM PST 24 58564760 ps
T698 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2743694197 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:14 PM PST 24 11167825 ps
T699 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.861057994 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:18 PM PST 24 31587697 ps
T700 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1841472240 Feb 28 04:17:07 PM PST 24 Feb 28 04:17:08 PM PST 24 218833461 ps
T701 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3133247179 Feb 28 04:17:08 PM PST 24 Feb 28 04:17:10 PM PST 24 309159683 ps
T134 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3037821474 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:17 PM PST 24 79364276 ps
T702 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.597760990 Feb 28 04:17:00 PM PST 24 Feb 28 04:17:01 PM PST 24 21948363 ps
T703 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2153187010 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 56099791 ps
T704 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.412055503 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:17 PM PST 24 56354880 ps
T705 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1610603996 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:00 PM PST 24 23329114 ps
T706 /workspace/coverage/cover_reg_top/13.hmac_intr_test.274246180 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:15 PM PST 24 14671534 ps
T707 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1831945133 Feb 28 04:18:43 PM PST 24 Feb 28 04:18:45 PM PST 24 69818008 ps
T708 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3528862666 Feb 28 04:17:13 PM PST 24 Feb 28 04:17:15 PM PST 24 174614799 ps
T709 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2794437881 Feb 28 04:17:11 PM PST 24 Feb 28 04:17:13 PM PST 24 182209797 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1220492114 Feb 28 04:17:12 PM PST 24 Feb 28 04:17:14 PM PST 24 38644905 ps
T710 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.6704593 Feb 28 04:17:12 PM PST 24 Feb 28 04:17:14 PM PST 24 561428638 ps
T94 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2721476567 Feb 28 04:17:02 PM PST 24 Feb 28 04:17:03 PM PST 24 12387338 ps
T711 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3362022633 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:18 PM PST 24 124677834 ps
T712 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4200079789 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:17 PM PST 24 42429279 ps
T139 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2191893630 Feb 28 04:17:11 PM PST 24 Feb 28 04:17:12 PM PST 24 193277480 ps
T713 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2411263104 Feb 28 04:17:15 PM PST 24 Feb 28 04:17:15 PM PST 24 23537570 ps
T714 /workspace/coverage/cover_reg_top/46.hmac_intr_test.589542805 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:21 PM PST 24 11750713 ps
T715 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.683321574 Feb 28 04:17:05 PM PST 24 Feb 28 04:17:06 PM PST 24 379860215 ps
T716 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3973530096 Feb 28 04:17:14 PM PST 24 Feb 28 04:17:17 PM PST 24 562734554 ps
T717 /workspace/coverage/cover_reg_top/5.hmac_intr_test.459604370 Feb 28 04:16:57 PM PST 24 Feb 28 04:16:58 PM PST 24 131900651 ps
T718 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2349554140 Feb 28 04:17:39 PM PST 24 Feb 28 04:17:40 PM PST 24 36987919 ps
T719 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1952854670 Feb 28 04:17:36 PM PST 24 Feb 28 04:17:37 PM PST 24 31818983 ps
T720 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.250268900 Feb 28 04:17:11 PM PST 24 Feb 28 04:17:13 PM PST 24 63561896 ps
T721 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1980458751 Feb 28 04:17:24 PM PST 24 Feb 28 04:17:25 PM PST 24 28193277 ps
T722 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2636515815 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 68522651 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4187856638 Feb 28 04:17:03 PM PST 24 Feb 28 04:17:12 PM PST 24 737473061 ps
T723 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3055072060 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:21 PM PST 24 53031922 ps
T724 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1214905926 Feb 28 04:16:59 PM PST 24 Feb 28 04:17:02 PM PST 24 593731433 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2365150383 Feb 28 04:17:06 PM PST 24 Feb 28 04:17:07 PM PST 24 93766753 ps
T725 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4074395306 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:24 PM PST 24 1488817533 ps
T726 /workspace/coverage/cover_reg_top/37.hmac_intr_test.770247618 Feb 28 04:17:21 PM PST 24 Feb 28 04:17:22 PM PST 24 15201609 ps
T727 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3289666976 Feb 28 04:17:18 PM PST 24 Feb 28 04:17:18 PM PST 24 28067791 ps
T728 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.333982462 Feb 28 04:17:26 PM PST 24 Feb 28 04:17:28 PM PST 24 60240930 ps
T729 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3262668872 Feb 28 04:16:59 PM PST 24 Feb 28 04:36:46 PM PST 24 537818795147 ps
T137 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1303716012 Feb 28 04:17:16 PM PST 24 Feb 28 04:17:18 PM PST 24 343078387 ps
T730 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2431421905 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:21 PM PST 24 53211540 ps
T731 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1281719816 Feb 28 04:16:58 PM PST 24 Feb 28 04:16:59 PM PST 24 21515821 ps
T732 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.499148120 Feb 28 04:17:06 PM PST 24 Feb 28 04:17:07 PM PST 24 15404986 ps
T733 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4285295886 Feb 28 04:17:20 PM PST 24 Feb 28 04:17:20 PM PST 24 49480838 ps
T734 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1175479211 Feb 28 04:17:22 PM PST 24 Feb 28 04:17:23 PM PST 24 193784221 ps

Test location /workspace/coverage/default/17.hmac_burst_wr.98159893
Short name T22
Test name
Test status
Simulation time 4982602261 ps
CPU time 46.75 seconds
Started Feb 28 04:43:32 PM PST 24
Finished Feb 28 04:44:20 PM PST 24
Peak memory 199504 kb
Host smart-c9b32039-ad79-4781-98f5-2700030b8aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98159893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.98159893
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.631501824
Short name T7
Test name
Test status
Simulation time 67677539850 ps
CPU time 527.95 seconds
Started Feb 28 04:45:23 PM PST 24
Finished Feb 28 04:54:11 PM PST 24
Peak memory 225880 kb
Host smart-1583fd30-6136-4fc2-964e-77f5bd1c58ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631501824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.631501824
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.304612540
Short name T64
Test name
Test status
Simulation time 12697031400 ps
CPU time 49.02 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 199532 kb
Host smart-6d57a0bb-671f-476a-a08d-fd0b9a682262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304612540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.304612540
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2376689542
Short name T5
Test name
Test status
Simulation time 201724699047 ps
CPU time 2259.69 seconds
Started Feb 28 04:42:44 PM PST 24
Finished Feb 28 05:20:25 PM PST 24
Peak memory 232248 kb
Host smart-2a52ce5e-0c7c-4d0c-a254-e4a7bed6c79c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376689542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2376689542
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.898110295
Short name T23
Test name
Test status
Simulation time 451295500 ps
CPU time 0.95 seconds
Started Feb 28 04:42:48 PM PST 24
Finished Feb 28 04:42:49 PM PST 24
Peak memory 217852 kb
Host smart-3a6475f8-df9b-47d1-b27b-c356bce75f20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898110295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.898110295
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2481972673
Short name T52
Test name
Test status
Simulation time 108076324 ps
CPU time 2.2 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:26 PM PST 24
Peak memory 198788 kb
Host smart-bf4aad26-7208-4bfe-aff7-7de4f4ab1d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481972673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2481972673
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.773102210
Short name T39
Test name
Test status
Simulation time 52405454866 ps
CPU time 1347.53 seconds
Started Feb 28 04:45:13 PM PST 24
Finished Feb 28 05:07:41 PM PST 24
Peak memory 247848 kb
Host smart-e828c01d-8c4f-44c1-9ebb-2a93ea1cee7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773102210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.773102210
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.1558540238
Short name T42
Test name
Test status
Simulation time 732664597509 ps
CPU time 1645.8 seconds
Started Feb 28 04:45:29 PM PST 24
Finished Feb 28 05:12:55 PM PST 24
Peak memory 240612 kb
Host smart-5772ac2c-5921-40f2-a176-0157cffa00a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558540238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.1558540238
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1024847057
Short name T83
Test name
Test status
Simulation time 27862720 ps
CPU time 0.76 seconds
Started Feb 28 04:16:55 PM PST 24
Finished Feb 28 04:16:56 PM PST 24
Peak memory 194500 kb
Host smart-f00eb4fe-d129-4824-8c8f-a77a684a9391
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024847057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1024847057
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2278266113
Short name T69
Test name
Test status
Simulation time 13352051310 ps
CPU time 190.68 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:47:14 PM PST 24
Peak memory 199568 kb
Host smart-af3cce1e-4388-44d5-95b9-00c3520a5c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278266113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2278266113
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.900673889
Short name T109
Test name
Test status
Simulation time 1364670121 ps
CPU time 70.72 seconds
Started Feb 28 04:45:05 PM PST 24
Finished Feb 28 04:46:16 PM PST 24
Peak memory 199396 kb
Host smart-74a9b70b-403c-4028-9e79-1055ab7ff4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900673889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.900673889
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.2420855844
Short name T479
Test name
Test status
Simulation time 139049967762 ps
CPU time 1749.33 seconds
Started Feb 28 04:45:41 PM PST 24
Finished Feb 28 05:14:50 PM PST 24
Peak memory 239084 kb
Host smart-2d88845c-cd2d-4cca-9ad4-f7d7accaf503
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420855844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.2420855844
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.1346959231
Short name T19
Test name
Test status
Simulation time 32199744034 ps
CPU time 333.85 seconds
Started Feb 28 04:45:19 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 240604 kb
Host smart-b2cf0d91-e7f1-407d-a47b-d95ea66433a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346959231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.1346959231
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2749634973
Short name T150
Test name
Test status
Simulation time 84376204 ps
CPU time 0.58 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 04:42:46 PM PST 24
Peak memory 193832 kb
Host smart-feb2f240-ab17-4795-9cc4-329959e78db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749634973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2749634973
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.204327655
Short name T135
Test name
Test status
Simulation time 183006834 ps
CPU time 1.62 seconds
Started Feb 28 04:17:32 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 198576 kb
Host smart-5d9e00a5-a581-4f59-9160-1f0017874b79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204327655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.204327655
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_error.387102171
Short name T32
Test name
Test status
Simulation time 3163291798 ps
CPU time 173.79 seconds
Started Feb 28 04:43:23 PM PST 24
Finished Feb 28 04:46:17 PM PST 24
Peak memory 199644 kb
Host smart-7d6facf2-7806-4f5b-a8e5-30607c877be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387102171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.387102171
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2902529403
Short name T133
Test name
Test status
Simulation time 2128696917 ps
CPU time 2.41 seconds
Started Feb 28 04:18:15 PM PST 24
Finished Feb 28 04:18:18 PM PST 24
Peak memory 198724 kb
Host smart-1073f8cf-bb2d-427e-9a3b-588ee8a5620e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902529403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2902529403
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2935318135
Short name T71
Test name
Test status
Simulation time 327849402919 ps
CPU time 1083.6 seconds
Started Feb 28 04:43:27 PM PST 24
Finished Feb 28 05:01:31 PM PST 24
Peak memory 240012 kb
Host smart-e521e728-c58e-431b-9202-1e0b6bd88850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935318135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2935318135
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1869514689
Short name T550
Test name
Test status
Simulation time 62796283951 ps
CPU time 199.85 seconds
Started Feb 28 04:43:32 PM PST 24
Finished Feb 28 04:46:53 PM PST 24
Peak memory 240628 kb
Host smart-9d19b175-85d4-406d-966f-613527059b2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869514689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1869514689
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.248097081
Short name T125
Test name
Test status
Simulation time 25074427534 ps
CPU time 795.55 seconds
Started Feb 28 04:45:44 PM PST 24
Finished Feb 28 04:59:00 PM PST 24
Peak memory 215920 kb
Host smart-c2c76eb1-49e3-4863-97d0-abe4d5b3cc81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248097081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.248097081
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3961636190
Short name T124
Test name
Test status
Simulation time 5498718020 ps
CPU time 46.74 seconds
Started Feb 28 04:43:43 PM PST 24
Finished Feb 28 04:44:30 PM PST 24
Peak memory 225140 kb
Host smart-e209620f-3df8-4d51-a548-d07dd44dca81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961636190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3961636190
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2815276944
Short name T127
Test name
Test status
Simulation time 1743344487 ps
CPU time 60.35 seconds
Started Feb 28 04:42:43 PM PST 24
Finished Feb 28 04:43:44 PM PST 24
Peak memory 226292 kb
Host smart-ffc55c80-d412-4246-b88a-f92b785c0fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815276944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2815276944
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2101468181
Short name T121
Test name
Test status
Simulation time 948648692 ps
CPU time 24.55 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:45:00 PM PST 24
Peak memory 199520 kb
Host smart-f9a9a766-2722-40a8-8acc-86150b771917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101468181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2101468181
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_error.2384488518
Short name T119
Test name
Test status
Simulation time 11248352684 ps
CPU time 148.06 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:47:11 PM PST 24
Peak memory 199416 kb
Host smart-cce01f40-e206-459b-bd09-e70ccfebeef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384488518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2384488518
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4099005651
Short name T74
Test name
Test status
Simulation time 310075505184 ps
CPU time 958.16 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 05:01:20 PM PST 24
Peak memory 215188 kb
Host smart-7411069d-46e2-47ce-ba4e-cd700ce8a379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099005651 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4099005651
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2217522991
Short name T43
Test name
Test status
Simulation time 5662370758 ps
CPU time 9.28 seconds
Started Feb 28 04:43:06 PM PST 24
Finished Feb 28 04:43:17 PM PST 24
Peak memory 215300 kb
Host smart-b5ed442f-2760-4830-a172-e403d5221759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217522991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2217522991
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3103648974
Short name T59
Test name
Test status
Simulation time 115903428 ps
CPU time 1.21 seconds
Started Feb 28 04:18:09 PM PST 24
Finished Feb 28 04:18:11 PM PST 24
Peak memory 198416 kb
Host smart-c04c03c1-0049-4956-bf6c-8a5a4fd13712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103648974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3103648974
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1220492114
Short name T90
Test name
Test status
Simulation time 38644905 ps
CPU time 1.8 seconds
Started Feb 28 04:17:12 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 192572 kb
Host smart-d226a9a6-e3fa-4db6-95e1-d9631637a0d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220492114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1220492114
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.256485133
Short name T682
Test name
Test status
Simulation time 659465204 ps
CPU time 9.18 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:08 PM PST 24
Peak memory 192600 kb
Host smart-464f38c3-ec78-4b93-aa60-bd43014dc2cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256485133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.256485133
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2365150383
Short name T92
Test name
Test status
Simulation time 93766753 ps
CPU time 0.97 seconds
Started Feb 28 04:17:06 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 194888 kb
Host smart-6768ac24-b3c8-4ce1-8e83-e1832d68e8a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365150383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2365150383
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4279588567
Short name T695
Test name
Test status
Simulation time 24547919 ps
CPU time 1.3 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:01 PM PST 24
Peak memory 198972 kb
Host smart-4f649238-8c53-439d-919a-554b0c25e3d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279588567 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4279588567
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.597760990
Short name T702
Test name
Test status
Simulation time 21948363 ps
CPU time 0.59 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:01 PM PST 24
Peak memory 194544 kb
Host smart-7cb0e038-f668-4191-89f8-20fde4102acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597760990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.597760990
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1672513982
Short name T689
Test name
Test status
Simulation time 72862850 ps
CPU time 0.56 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:01 PM PST 24
Peak memory 184160 kb
Host smart-255e6b8d-ba96-409d-827e-b59ef37ba3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672513982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1672513982
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3953955801
Short name T662
Test name
Test status
Simulation time 71332358 ps
CPU time 1.44 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:02 PM PST 24
Peak memory 197388 kb
Host smart-31d8e123-7e80-4728-9066-71f22f93d198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953955801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3953955801
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.683321574
Short name T715
Test name
Test status
Simulation time 379860215 ps
CPU time 1.33 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:06 PM PST 24
Peak memory 199072 kb
Host smart-2fdc83bf-5c55-4c2d-bbd3-92ee349db7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683321574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.683321574
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4148204498
Short name T54
Test name
Test status
Simulation time 207130053 ps
CPU time 1.2 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:00 PM PST 24
Peak memory 198084 kb
Host smart-b5b1c094-7165-437a-81bf-20cdecc54bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148204498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4148204498
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1497706389
Short name T93
Test name
Test status
Simulation time 561583970 ps
CPU time 2.56 seconds
Started Feb 28 04:16:56 PM PST 24
Finished Feb 28 04:16:59 PM PST 24
Peak memory 192576 kb
Host smart-6e300ebc-1081-43d8-b988-2525dc630ebc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497706389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1497706389
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4187856638
Short name T91
Test name
Test status
Simulation time 737473061 ps
CPU time 8.03 seconds
Started Feb 28 04:17:03 PM PST 24
Finished Feb 28 04:17:12 PM PST 24
Peak memory 184436 kb
Host smart-44a1b49e-0a6c-4596-8903-801d61aab78f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187856638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4187856638
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2300680507
Short name T664
Test name
Test status
Simulation time 387538819928 ps
CPU time 883.76 seconds
Started Feb 28 04:17:09 PM PST 24
Finished Feb 28 04:31:53 PM PST 24
Peak memory 210820 kb
Host smart-8b1db150-b15e-4420-ab83-71ae7051ff25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300680507 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2300680507
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.499148120
Short name T732
Test name
Test status
Simulation time 15404986 ps
CPU time 0.79 seconds
Started Feb 28 04:17:06 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 195200 kb
Host smart-779ab140-1053-49c1-b804-43bb91251bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499148120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.499148120
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1610603996
Short name T705
Test name
Test status
Simulation time 23329114 ps
CPU time 0.57 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:00 PM PST 24
Peak memory 184148 kb
Host smart-ffc2d1ff-2db2-44cd-bef6-06f280bde8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610603996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1610603996
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1841854384
Short name T621
Test name
Test status
Simulation time 108396011 ps
CPU time 0.84 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:01 PM PST 24
Peak memory 192360 kb
Host smart-d4eec449-a7d9-4049-9cc8-88aa8b4c5938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841854384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1841854384
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2003235435
Short name T616
Test name
Test status
Simulation time 162066095 ps
CPU time 3.29 seconds
Started Feb 28 04:16:58 PM PST 24
Finished Feb 28 04:17:02 PM PST 24
Peak memory 199132 kb
Host smart-f2f65c12-4b86-4f6a-8a83-845690f9bfd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003235435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2003235435
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1290368492
Short name T131
Test name
Test status
Simulation time 44658177 ps
CPU time 1.18 seconds
Started Feb 28 04:16:56 PM PST 24
Finished Feb 28 04:16:58 PM PST 24
Peak memory 198376 kb
Host smart-19cf5837-4026-417f-8e66-d0861effb0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290368492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1290368492
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.991312485
Short name T642
Test name
Test status
Simulation time 135740135 ps
CPU time 1.04 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 198844 kb
Host smart-73c1cf69-b2b6-4968-9533-e0cb81481cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991312485 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.991312485
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3706906450
Short name T81
Test name
Test status
Simulation time 14378232 ps
CPU time 0.64 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 194280 kb
Host smart-e67bfaae-9499-44da-834f-0fe7e63de4db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706906450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3706906450
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2896642763
Short name T687
Test name
Test status
Simulation time 34045786 ps
CPU time 0.59 seconds
Started Feb 28 04:17:10 PM PST 24
Finished Feb 28 04:17:11 PM PST 24
Peak memory 184120 kb
Host smart-1e525cb3-fedf-46e6-bb9e-441016496cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896642763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2896642763
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2354470951
Short name T685
Test name
Test status
Simulation time 23708100 ps
CPU time 1 seconds
Started Feb 28 04:17:46 PM PST 24
Finished Feb 28 04:17:48 PM PST 24
Peak memory 197312 kb
Host smart-33bf0b9b-9997-4077-b9d4-1b0c9670915f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354470951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2354470951
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.496505755
Short name T645
Test name
Test status
Simulation time 123288222 ps
CPU time 1.56 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 198972 kb
Host smart-44f314b7-ff00-48b4-bcc0-a7791673dcf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496505755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.496505755
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3037821474
Short name T134
Test name
Test status
Simulation time 79364276 ps
CPU time 1.71 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 198624 kb
Host smart-11d91f32-824a-4e49-93fb-9d5bb252cca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037821474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3037821474
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1925506054
Short name T634
Test name
Test status
Simulation time 186611912 ps
CPU time 2.19 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 198992 kb
Host smart-346fe854-b719-4be5-9941-30b62690ec1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925506054 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1925506054
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2581047386
Short name T679
Test name
Test status
Simulation time 33148364 ps
CPU time 0.67 seconds
Started Feb 28 04:17:24 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 194700 kb
Host smart-23822159-a3e0-4036-9224-ec52eb54a519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581047386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2581047386
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2517417914
Short name T690
Test name
Test status
Simulation time 14853556 ps
CPU time 0.63 seconds
Started Feb 28 04:17:08 PM PST 24
Finished Feb 28 04:17:09 PM PST 24
Peak memory 184152 kb
Host smart-29eb04fa-a822-4317-80f8-d16ed232eef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517417914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2517417914
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4000685096
Short name T676
Test name
Test status
Simulation time 421538458 ps
CPU time 1.14 seconds
Started Feb 28 04:17:32 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 192624 kb
Host smart-d5b5e4f7-fec6-417f-892c-7f9cfa29c244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000685096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4000685096
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2794437881
Short name T709
Test name
Test status
Simulation time 182209797 ps
CPU time 1.32 seconds
Started Feb 28 04:17:11 PM PST 24
Finished Feb 28 04:17:13 PM PST 24
Peak memory 199044 kb
Host smart-7fb3a3f3-dfb2-4ed9-8f15-dc55755f4e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794437881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2794437881
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3918270521
Short name T649
Test name
Test status
Simulation time 130498124 ps
CPU time 1.7 seconds
Started Feb 28 04:17:48 PM PST 24
Finished Feb 28 04:17:52 PM PST 24
Peak memory 199076 kb
Host smart-af8b91bf-c4dc-4415-acd0-0d1a6c505dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918270521 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3918270521
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1380570335
Short name T78
Test name
Test status
Simulation time 51055600 ps
CPU time 0.6 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 194356 kb
Host smart-0ff06a46-f10c-4458-9c1c-c7ed2c68767e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380570335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1380570335
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3170909404
Short name T686
Test name
Test status
Simulation time 14617160 ps
CPU time 0.57 seconds
Started Feb 28 04:17:45 PM PST 24
Finished Feb 28 04:17:45 PM PST 24
Peak memory 184156 kb
Host smart-e949c27f-4d38-4978-8b7a-4ff605c7da84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170909404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3170909404
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.861057994
Short name T699
Test name
Test status
Simulation time 31587697 ps
CPU time 1.26 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 192616 kb
Host smart-8ffd3d72-7239-433e-ba8c-02be283a0241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861057994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.861057994
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3055072060
Short name T723
Test name
Test status
Simulation time 53031922 ps
CPU time 2.52 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 199000 kb
Host smart-96d3cedb-c669-41f2-99fa-2512fb32cfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055072060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3055072060
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.120641842
Short name T681
Test name
Test status
Simulation time 101603526710 ps
CPU time 202.74 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:20:40 PM PST 24
Peak memory 199332 kb
Host smart-338d54e8-d2f4-4146-9d4e-dc8373952be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120641842 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.120641842
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.147012012
Short name T58
Test name
Test status
Simulation time 72502862 ps
CPU time 0.67 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 194916 kb
Host smart-586e4982-841c-4d4e-b30e-fa46d907ca57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147012012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.147012012
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.274246180
Short name T706
Test name
Test status
Simulation time 14671534 ps
CPU time 0.6 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184152 kb
Host smart-e3b61dcd-8ee7-4fc0-b15d-01fd88dfb236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274246180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.274246180
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2699850275
Short name T665
Test name
Test status
Simulation time 64787444 ps
CPU time 0.72 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 192432 kb
Host smart-b45fc10c-aff5-4f42-8540-259e438ee8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699850275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2699850275
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3006947132
Short name T657
Test name
Test status
Simulation time 481673619 ps
CPU time 2.81 seconds
Started Feb 28 04:17:12 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 199020 kb
Host smart-94b82ca7-50a7-4079-b7c8-c3621574b53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006947132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3006947132
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1343016825
Short name T132
Test name
Test status
Simulation time 434053486 ps
CPU time 1.88 seconds
Started Feb 28 04:18:30 PM PST 24
Finished Feb 28 04:18:32 PM PST 24
Peak memory 198652 kb
Host smart-aeaad38b-d2f2-4ae8-8102-47592fb8d7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343016825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1343016825
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2153455007
Short name T632
Test name
Test status
Simulation time 50263043 ps
CPU time 1.52 seconds
Started Feb 28 04:17:24 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 199088 kb
Host smart-4648cc1d-7171-48ac-b594-4344871f1dbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153455007 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2153455007
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.356527803
Short name T87
Test name
Test status
Simulation time 14119265 ps
CPU time 0.61 seconds
Started Feb 28 04:17:53 PM PST 24
Finished Feb 28 04:17:54 PM PST 24
Peak memory 194352 kb
Host smart-30b6e6dd-a7e5-4816-bd93-b3467b2d0e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356527803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.356527803
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1866491701
Short name T604
Test name
Test status
Simulation time 15182751 ps
CPU time 0.55 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184124 kb
Host smart-fe82d316-acf0-4128-a0ff-2de6d0ed1fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866491701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1866491701
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3725453538
Short name T651
Test name
Test status
Simulation time 51928465 ps
CPU time 0.78 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 192428 kb
Host smart-ddf61212-25a2-4c05-879d-9484a76e2256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725453538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3725453538
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2725462933
Short name T675
Test name
Test status
Simulation time 727706018 ps
CPU time 3.51 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 199060 kb
Host smart-0cbb411b-5dce-4e1e-9f06-ea85e616113b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725462933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2725462933
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.412055503
Short name T704
Test name
Test status
Simulation time 56354880 ps
CPU time 1.13 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 198044 kb
Host smart-79b0da2b-5a76-4e7e-846b-08241758e692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412055503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.412055503
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1312535990
Short name T669
Test name
Test status
Simulation time 45738002 ps
CPU time 2.79 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 199012 kb
Host smart-0880421f-4779-4baf-a088-250749ed9c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312535990 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1312535990
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1952854670
Short name T719
Test name
Test status
Simulation time 31818983 ps
CPU time 0.61 seconds
Started Feb 28 04:17:36 PM PST 24
Finished Feb 28 04:17:37 PM PST 24
Peak memory 194728 kb
Host smart-55f18f81-7e2f-48b5-9ba8-753af8a3d22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952854670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1952854670
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1402050165
Short name T606
Test name
Test status
Simulation time 16624165 ps
CPU time 0.62 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184164 kb
Host smart-5747a759-7de8-40ed-bf6c-2072e00c0a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402050165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1402050165
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3859476457
Short name T57
Test name
Test status
Simulation time 98174533 ps
CPU time 0.81 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:16 PM PST 24
Peak memory 192416 kb
Host smart-8248fb54-8e09-48a5-af20-d51e4e52b6c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859476457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3859476457
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1149258423
Short name T671
Test name
Test status
Simulation time 361737172 ps
CPU time 3.4 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 199104 kb
Host smart-8cf4293f-1d80-4a22-95bc-1aee6dbdd387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149258423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1149258423
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1303716012
Short name T137
Test name
Test status
Simulation time 343078387 ps
CPU time 1.73 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 198700 kb
Host smart-f04627dc-6b99-46d8-a0b1-34502c3fc488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303716012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1303716012
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1831945133
Short name T707
Test name
Test status
Simulation time 69818008 ps
CPU time 1.78 seconds
Started Feb 28 04:18:43 PM PST 24
Finished Feb 28 04:18:45 PM PST 24
Peak memory 198268 kb
Host smart-913b864f-235c-4fc4-be59-09be0cef888d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831945133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1831945133
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2731681255
Short name T636
Test name
Test status
Simulation time 34670297 ps
CPU time 0.66 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 194488 kb
Host smart-31e9f350-ae05-4ccb-83fb-73c6a789c14a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731681255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2731681255
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3589285850
Short name T635
Test name
Test status
Simulation time 22793432 ps
CPU time 0.6 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 184148 kb
Host smart-7d977eca-0ead-4ab0-8a25-db8ccf145a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589285850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3589285850
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3362022633
Short name T711
Test name
Test status
Simulation time 124677834 ps
CPU time 0.83 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 192432 kb
Host smart-aff6339e-8069-4433-9f9c-1fa9462ae8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362022633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3362022633
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.331473041
Short name T683
Test name
Test status
Simulation time 661710043 ps
CPU time 3.33 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 199016 kb
Host smart-67583118-3051-4a22-b1a0-5b7e6cb8aab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331473041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.331473041
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1901579839
Short name T53
Test name
Test status
Simulation time 120465470 ps
CPU time 1.15 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 198416 kb
Host smart-1b750136-2901-497f-8620-b82f15680841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901579839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1901579839
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4074395306
Short name T725
Test name
Test status
Simulation time 1488817533 ps
CPU time 2.05 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:24 PM PST 24
Peak memory 199044 kb
Host smart-8245c4ab-42ca-4788-86eb-1fd41c2b6c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074395306 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4074395306
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.509476713
Short name T640
Test name
Test status
Simulation time 16383683 ps
CPU time 0.65 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:22 PM PST 24
Peak memory 194628 kb
Host smart-5af7c85c-0d21-4e93-8e0b-6e5a57ab4fea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509476713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.509476713
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.869150837
Short name T688
Test name
Test status
Simulation time 14669460 ps
CPU time 0.7 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184092 kb
Host smart-b04925d3-f07c-4430-8f8c-cb64931d2674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869150837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.869150837
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1712534976
Short name T674
Test name
Test status
Simulation time 59786426 ps
CPU time 1.29 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 192624 kb
Host smart-aa97d982-0653-40d9-9244-0e3df3981b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712534976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1712534976
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.501057904
Short name T603
Test name
Test status
Simulation time 133380898 ps
CPU time 1.13 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 198844 kb
Host smart-691c13cd-89f5-4024-98aa-5e6e97de969a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501057904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.501057904
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3745236339
Short name T652
Test name
Test status
Simulation time 324777122 ps
CPU time 2.52 seconds
Started Feb 28 04:17:11 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 198600 kb
Host smart-1424fadf-f5aa-40a7-8ca1-8f37fedff016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745236339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3745236339
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1583919252
Short name T644
Test name
Test status
Simulation time 189540514 ps
CPU time 2.03 seconds
Started Feb 28 04:17:38 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 199056 kb
Host smart-2001a238-5c04-40a7-b015-62a99fbabc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583919252 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1583919252
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3715621390
Short name T56
Test name
Test status
Simulation time 18824315 ps
CPU time 0.57 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 194248 kb
Host smart-3df472b7-93a7-4eac-a8f0-945ab7911644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715621390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3715621390
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1805503792
Short name T629
Test name
Test status
Simulation time 39900981 ps
CPU time 0.57 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 183980 kb
Host smart-413db61a-4a71-41f3-ac49-e158c6b6d6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805503792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1805503792
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1343058492
Short name T631
Test name
Test status
Simulation time 53180242 ps
CPU time 0.76 seconds
Started Feb 28 04:19:03 PM PST 24
Finished Feb 28 04:19:04 PM PST 24
Peak memory 192456 kb
Host smart-e4f6e9f6-517f-43ff-b140-9dc50e03989c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343058492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1343058492
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3199402245
Short name T609
Test name
Test status
Simulation time 30930544 ps
CPU time 1.63 seconds
Started Feb 28 04:17:35 PM PST 24
Finished Feb 28 04:17:37 PM PST 24
Peak memory 199004 kb
Host smart-b7a497f9-3a19-4fe4-bdfd-59473812160b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199402245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3199402245
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4200079789
Short name T712
Test name
Test status
Simulation time 42429279 ps
CPU time 1.06 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 197884 kb
Host smart-c8d9cf43-b73e-476a-8178-dd79314e262f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200079789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4200079789
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4065394234
Short name T630
Test name
Test status
Simulation time 90923225 ps
CPU time 1.7 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:16 PM PST 24
Peak memory 199124 kb
Host smart-06c5f12f-8de0-41b7-9cbb-12a639e4488c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065394234 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4065394234
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2570519695
Short name T84
Test name
Test status
Simulation time 16283165 ps
CPU time 0.7 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 194652 kb
Host smart-ff4be8ab-989b-462e-8a33-a121871023a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570519695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2570519695
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3718440206
Short name T628
Test name
Test status
Simulation time 44695042 ps
CPU time 0.53 seconds
Started Feb 28 04:17:33 PM PST 24
Finished Feb 28 04:17:34 PM PST 24
Peak memory 184048 kb
Host smart-8d569cfd-c235-4a9b-8cba-b4c1d8096464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718440206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3718440206
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1175479211
Short name T734
Test name
Test status
Simulation time 193784221 ps
CPU time 1.12 seconds
Started Feb 28 04:17:22 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 192624 kb
Host smart-00962e9d-2827-4315-ac77-c72a6b741de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175479211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1175479211
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.239045257
Short name T661
Test name
Test status
Simulation time 117246694 ps
CPU time 3.09 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 199000 kb
Host smart-39cdc78f-b165-4f39-8e9f-681bbbfb6969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239045257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.239045257
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.109827589
Short name T89
Test name
Test status
Simulation time 23118156 ps
CPU time 1.18 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:01 PM PST 24
Peak memory 192656 kb
Host smart-01fa66a0-fd6f-4b98-88dd-a81bcc5eced2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109827589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.109827589
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1875863380
Short name T667
Test name
Test status
Simulation time 2486338462 ps
CPU time 10.06 seconds
Started Feb 28 04:17:06 PM PST 24
Finished Feb 28 04:17:16 PM PST 24
Peak memory 192840 kb
Host smart-9c72e773-9976-4980-af17-6f7cfd1cf5a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875863380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1875863380
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3766807090
Short name T654
Test name
Test status
Simulation time 95170898 ps
CPU time 0.66 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 194356 kb
Host smart-b63fcd11-e873-4016-bb16-966b7aa5bc2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766807090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3766807090
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1138416746
Short name T672
Test name
Test status
Simulation time 89439748 ps
CPU time 3.03 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:16 PM PST 24
Peak memory 199104 kb
Host smart-41d0b04b-f1e5-49d3-b51e-6954497123ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138416746 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1138416746
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1896833244
Short name T641
Test name
Test status
Simulation time 51824642 ps
CPU time 0.68 seconds
Started Feb 28 04:16:57 PM PST 24
Finished Feb 28 04:16:59 PM PST 24
Peak memory 194228 kb
Host smart-4e3354a1-75c7-4578-a937-93533503e357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896833244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1896833244
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3286663544
Short name T610
Test name
Test status
Simulation time 47569922 ps
CPU time 0.58 seconds
Started Feb 28 04:16:56 PM PST 24
Finished Feb 28 04:16:57 PM PST 24
Peak memory 184088 kb
Host smart-14556e11-0f0a-420d-984e-ad9cf0c7db32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286663544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3286663544
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.797991585
Short name T650
Test name
Test status
Simulation time 28876241 ps
CPU time 1.26 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 192628 kb
Host smart-5ee1e676-01cd-4058-b1af-04b5e4256491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797991585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.797991585
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1214905926
Short name T724
Test name
Test status
Simulation time 593731433 ps
CPU time 2.81 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:02 PM PST 24
Peak memory 199012 kb
Host smart-82024239-c20e-46bc-892d-69f7d49af336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214905926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1214905926
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.6704593
Short name T710
Test name
Test status
Simulation time 561428638 ps
CPU time 2.25 seconds
Started Feb 28 04:17:12 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 198672 kb
Host smart-a9b7ef45-6587-4bc5-aef1-cf3492598c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6704593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.6704593
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2934392306
Short name T611
Test name
Test status
Simulation time 12175514 ps
CPU time 0.58 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 184256 kb
Host smart-29bd3211-bb41-4c72-b530-d729e433e51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934392306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2934392306
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1673911853
Short name T647
Test name
Test status
Simulation time 152927817 ps
CPU time 0.59 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 184240 kb
Host smart-588aed71-aaaa-43c1-9c17-38bfb62e41f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673911853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1673911853
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.548932158
Short name T646
Test name
Test status
Simulation time 14982163 ps
CPU time 0.58 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184164 kb
Host smart-242c53a7-3716-47ef-9534-b12280f64e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548932158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.548932158
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1842200738
Short name T691
Test name
Test status
Simulation time 42544499 ps
CPU time 0.61 seconds
Started Feb 28 04:17:31 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 184276 kb
Host smart-c0136f3d-44b2-45b8-b9ad-9012c32017a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842200738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1842200738
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1187511283
Short name T655
Test name
Test status
Simulation time 16713096 ps
CPU time 0.62 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 184272 kb
Host smart-84b75239-d606-4215-84d3-58b53276d719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187511283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1187511283
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2126170649
Short name T638
Test name
Test status
Simulation time 18328589 ps
CPU time 0.65 seconds
Started Feb 28 04:17:23 PM PST 24
Finished Feb 28 04:17:23 PM PST 24
Peak memory 184168 kb
Host smart-28142125-9bc1-454c-84de-ce87ca2b1a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126170649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2126170649
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4285295886
Short name T733
Test name
Test status
Simulation time 49480838 ps
CPU time 0.6 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 184116 kb
Host smart-97480939-b3e0-4732-87b2-011342970d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285295886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4285295886
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1055638351
Short name T648
Test name
Test status
Simulation time 19513206 ps
CPU time 0.59 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184204 kb
Host smart-13f68255-f32f-4bea-99b3-fa0f0b1d33c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055638351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1055638351
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.435903514
Short name T622
Test name
Test status
Simulation time 29938106 ps
CPU time 0.63 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 184288 kb
Host smart-2f7eafb0-4cc8-498b-aad1-e14ecabdc216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435903514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.435903514
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1766577323
Short name T618
Test name
Test status
Simulation time 14157539 ps
CPU time 0.56 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 184132 kb
Host smart-091df2f8-b0f1-4723-88c9-b26523d75a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766577323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1766577323
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2895126627
Short name T625
Test name
Test status
Simulation time 24554479 ps
CPU time 1.21 seconds
Started Feb 28 04:17:07 PM PST 24
Finished Feb 28 04:17:08 PM PST 24
Peak memory 184456 kb
Host smart-dc80ad24-50ac-492b-b918-aa7436728e2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895126627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2895126627
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.860137727
Short name T639
Test name
Test status
Simulation time 848861261 ps
CPU time 3.29 seconds
Started Feb 28 04:17:08 PM PST 24
Finished Feb 28 04:17:11 PM PST 24
Peak memory 192620 kb
Host smart-3af51f83-2869-4e61-b44c-425572190895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860137727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.860137727
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3582787288
Short name T619
Test name
Test status
Simulation time 37624932 ps
CPU time 0.69 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:06 PM PST 24
Peak memory 194240 kb
Host smart-0c633b07-f652-4357-b8bb-f7c4c986e664
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582787288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3582787288
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1147204727
Short name T659
Test name
Test status
Simulation time 224262745 ps
CPU time 2.45 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:02 PM PST 24
Peak memory 199084 kb
Host smart-779dac5d-3753-4eea-aef1-6246fc228c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147204727 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1147204727
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1281719816
Short name T731
Test name
Test status
Simulation time 21515821 ps
CPU time 0.69 seconds
Started Feb 28 04:16:58 PM PST 24
Finished Feb 28 04:16:59 PM PST 24
Peak memory 194716 kb
Host smart-8d9e6fc7-6076-40ca-a412-604f02bd0f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281719816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1281719816
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3796574001
Short name T612
Test name
Test status
Simulation time 14371513 ps
CPU time 0.59 seconds
Started Feb 28 04:17:07 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 184160 kb
Host smart-14691fa7-a1c0-41cc-8336-b3c568536545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796574001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3796574001
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1805091136
Short name T620
Test name
Test status
Simulation time 173861928 ps
CPU time 0.84 seconds
Started Feb 28 04:17:09 PM PST 24
Finished Feb 28 04:17:10 PM PST 24
Peak memory 192404 kb
Host smart-303822af-63ac-410f-848c-625a9ea4ae29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805091136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1805091136
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3372048706
Short name T670
Test name
Test status
Simulation time 30923022 ps
CPU time 1.62 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 198976 kb
Host smart-e2c41ff9-90b2-4e6f-83ff-60f59419125c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372048706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3372048706
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2065293256
Short name T136
Test name
Test status
Simulation time 412134059 ps
CPU time 2.61 seconds
Started Feb 28 04:17:00 PM PST 24
Finished Feb 28 04:17:03 PM PST 24
Peak memory 198984 kb
Host smart-da96736e-440f-441b-9f4a-ffa855ef1308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065293256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2065293256
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4186041710
Short name T615
Test name
Test status
Simulation time 33720994 ps
CPU time 0.58 seconds
Started Feb 28 04:17:19 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 184156 kb
Host smart-4f7e4375-6f48-4e56-8625-0db315b8bbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186041710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4186041710
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3859934074
Short name T624
Test name
Test status
Simulation time 55380020 ps
CPU time 0.6 seconds
Started Feb 28 04:17:30 PM PST 24
Finished Feb 28 04:17:31 PM PST 24
Peak memory 184156 kb
Host smart-e3d050ad-4cd7-4da1-b151-3201ce2cd3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859934074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3859934074
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1039761394
Short name T694
Test name
Test status
Simulation time 15720797 ps
CPU time 0.56 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 184092 kb
Host smart-18f4d6ba-447b-44a6-84f2-576d6207f186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039761394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1039761394
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2411263104
Short name T713
Test name
Test status
Simulation time 23537570 ps
CPU time 0.61 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184164 kb
Host smart-c41ad9e5-a579-45d2-a232-ad9278277207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411263104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2411263104
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2153187010
Short name T703
Test name
Test status
Simulation time 56099791 ps
CPU time 0.64 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184120 kb
Host smart-068138c8-09b2-452a-aad7-3a1262fdcc43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153187010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2153187010
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3543753420
Short name T614
Test name
Test status
Simulation time 16882107 ps
CPU time 0.58 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 184164 kb
Host smart-a0b30bcf-6164-4371-b49a-006c498177e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543753420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3543753420
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3458352238
Short name T668
Test name
Test status
Simulation time 10801345 ps
CPU time 0.58 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184116 kb
Host smart-c41914b6-2012-4bdf-b7af-faff277556b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458352238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3458352238
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.770247618
Short name T726
Test name
Test status
Simulation time 15201609 ps
CPU time 0.58 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:22 PM PST 24
Peak memory 184128 kb
Host smart-2cc57782-db3a-4cb7-8d00-7654a5b2964b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770247618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.770247618
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1169124752
Short name T643
Test name
Test status
Simulation time 29538841 ps
CPU time 0.57 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:16 PM PST 24
Peak memory 184172 kb
Host smart-51acbaf0-1fb5-4085-9585-471d8b9025f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169124752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1169124752
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4055267944
Short name T608
Test name
Test status
Simulation time 44599976 ps
CPU time 0.58 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184168 kb
Host smart-d64c22d2-913f-4574-a80d-1d884e7c4056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055267944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4055267944
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3733201186
Short name T86
Test name
Test status
Simulation time 212385261 ps
CPU time 1.87 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 192552 kb
Host smart-37d7d707-18a2-4b2a-b367-eb7d48170ea2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733201186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3733201186
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2573799620
Short name T693
Test name
Test status
Simulation time 130075227 ps
CPU time 5.45 seconds
Started Feb 28 04:17:15 PM PST 24
Finished Feb 28 04:17:20 PM PST 24
Peak memory 192600 kb
Host smart-a8057204-65f6-43c8-a990-0dafb8a44af9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573799620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2573799620
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1646715097
Short name T88
Test name
Test status
Simulation time 65507664 ps
CPU time 0.75 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:17:00 PM PST 24
Peak memory 194376 kb
Host smart-9d1ad15d-d43a-4d64-84fe-cd47569c54ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646715097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1646715097
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3262668872
Short name T729
Test name
Test status
Simulation time 537818795147 ps
CPU time 1186.72 seconds
Started Feb 28 04:16:59 PM PST 24
Finished Feb 28 04:36:46 PM PST 24
Peak memory 218924 kb
Host smart-f87c676e-22d0-4320-a12b-6090c2c90f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262668872 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3262668872
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1452833908
Short name T673
Test name
Test status
Simulation time 43491783 ps
CPU time 0.63 seconds
Started Feb 28 04:17:16 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 194104 kb
Host smart-32b4f590-c517-46f7-9e90-a7cff1f8cc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452833908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1452833908
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2133469950
Short name T677
Test name
Test status
Simulation time 43910850 ps
CPU time 0.56 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:05 PM PST 24
Peak memory 184120 kb
Host smart-df86320b-fb3a-40de-9c95-d950f870a06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133469950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2133469950
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.781927778
Short name T680
Test name
Test status
Simulation time 219592944 ps
CPU time 1.34 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:22 PM PST 24
Peak memory 197448 kb
Host smart-ea3d4668-6600-4dbb-9754-c75d77d4c11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781927778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.781927778
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3002218179
Short name T623
Test name
Test status
Simulation time 122540675 ps
CPU time 1.73 seconds
Started Feb 28 04:16:58 PM PST 24
Finished Feb 28 04:17:00 PM PST 24
Peak memory 198996 kb
Host smart-91a9ccd1-9d00-4708-9b82-670e7113c4d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002218179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3002218179
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2556939244
Short name T138
Test name
Test status
Simulation time 408212776 ps
CPU time 1.76 seconds
Started Feb 28 04:16:58 PM PST 24
Finished Feb 28 04:17:00 PM PST 24
Peak memory 198424 kb
Host smart-14184a5b-5ca0-4297-ad04-526a89213f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556939244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2556939244
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1980458751
Short name T721
Test name
Test status
Simulation time 28193277 ps
CPU time 0.57 seconds
Started Feb 28 04:17:24 PM PST 24
Finished Feb 28 04:17:25 PM PST 24
Peak memory 184132 kb
Host smart-a66432dd-713f-40b8-87df-ea5900ff2901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980458751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1980458751
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2743694197
Short name T698
Test name
Test status
Simulation time 11167825 ps
CPU time 0.56 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 184168 kb
Host smart-6f98a84c-568d-4a35-8e74-e896db453a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743694197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2743694197
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1340967758
Short name T656
Test name
Test status
Simulation time 153968226 ps
CPU time 0.6 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184132 kb
Host smart-6953093a-42f8-4a12-8783-1af91d980224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340967758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1340967758
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1504044019
Short name T678
Test name
Test status
Simulation time 68997355 ps
CPU time 0.59 seconds
Started Feb 28 04:17:23 PM PST 24
Finished Feb 28 04:17:24 PM PST 24
Peak memory 184160 kb
Host smart-44e8ec21-1b1d-4d1f-88e1-7d278bcce4fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504044019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1504044019
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3289666976
Short name T727
Test name
Test status
Simulation time 28067791 ps
CPU time 0.58 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 184140 kb
Host smart-5316e6af-5b68-4088-9843-4090781935e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289666976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3289666976
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2636515815
Short name T722
Test name
Test status
Simulation time 68522651 ps
CPU time 0.55 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 184156 kb
Host smart-eb5a222f-3973-4bb7-abea-4d6f7b7e8023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636515815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2636515815
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.589542805
Short name T714
Test name
Test status
Simulation time 11750713 ps
CPU time 0.54 seconds
Started Feb 28 04:17:21 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 184088 kb
Host smart-f0046fa2-439c-437a-8162-6f05f1e6933a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589542805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.589542805
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4083170810
Short name T692
Test name
Test status
Simulation time 76915559 ps
CPU time 0.56 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 184092 kb
Host smart-4a5d0fc3-bfd1-4467-be75-1e322dd187c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083170810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4083170810
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2431421905
Short name T730
Test name
Test status
Simulation time 53211540 ps
CPU time 0.57 seconds
Started Feb 28 04:17:20 PM PST 24
Finished Feb 28 04:17:21 PM PST 24
Peak memory 184140 kb
Host smart-4aa99936-ba38-48e4-991e-4a431d8bfafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431421905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2431421905
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2640496821
Short name T697
Test name
Test status
Simulation time 58564760 ps
CPU time 0.55 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 184096 kb
Host smart-8c822f1e-1be6-4ae7-b875-ee015f94c819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640496821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2640496821
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3609945951
Short name T607
Test name
Test status
Simulation time 79493557 ps
CPU time 1.24 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 199012 kb
Host smart-3b5760da-9edb-448c-a3a4-6d1f304450c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609945951 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3609945951
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2085052526
Short name T85
Test name
Test status
Simulation time 46216072 ps
CPU time 0.71 seconds
Started Feb 28 04:17:05 PM PST 24
Finished Feb 28 04:17:06 PM PST 24
Peak memory 194664 kb
Host smart-d1871775-0158-419d-9bc4-141ca1ce562d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085052526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2085052526
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.459604370
Short name T717
Test name
Test status
Simulation time 131900651 ps
CPU time 0.6 seconds
Started Feb 28 04:16:57 PM PST 24
Finished Feb 28 04:16:58 PM PST 24
Peak memory 184116 kb
Host smart-a3dbf8af-7ad2-4d1b-ba48-9c91f8509d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459604370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.459604370
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2449959730
Short name T684
Test name
Test status
Simulation time 54671753 ps
CPU time 1.08 seconds
Started Feb 28 04:17:10 PM PST 24
Finished Feb 28 04:17:12 PM PST 24
Peak memory 197080 kb
Host smart-d6cae9a8-842c-47c3-bc76-10a0b2cb5380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449959730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2449959730
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4145517011
Short name T660
Test name
Test status
Simulation time 38473093 ps
CPU time 2.15 seconds
Started Feb 28 04:17:07 PM PST 24
Finished Feb 28 04:17:09 PM PST 24
Peak memory 199076 kb
Host smart-71e2a940-053c-4fe7-8787-936d48133f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145517011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4145517011
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1841472240
Short name T700
Test name
Test status
Simulation time 218833461 ps
CPU time 1.15 seconds
Started Feb 28 04:17:07 PM PST 24
Finished Feb 28 04:17:08 PM PST 24
Peak memory 198320 kb
Host smart-a661fad9-6ecc-473a-b6e2-ea9450260330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841472240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1841472240
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3684841464
Short name T613
Test name
Test status
Simulation time 91325295 ps
CPU time 2.28 seconds
Started Feb 28 04:17:09 PM PST 24
Finished Feb 28 04:17:12 PM PST 24
Peak memory 199020 kb
Host smart-6fcca961-e2d0-4362-a696-27fcdd33cd8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684841464 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3684841464
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3704006990
Short name T80
Test name
Test status
Simulation time 32417842 ps
CPU time 0.66 seconds
Started Feb 28 04:17:11 PM PST 24
Finished Feb 28 04:17:12 PM PST 24
Peak memory 194636 kb
Host smart-57c8b927-d0b0-4a8c-afcf-af3c56d4f92e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704006990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3704006990
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.325434744
Short name T653
Test name
Test status
Simulation time 12719380 ps
CPU time 0.57 seconds
Started Feb 28 04:17:09 PM PST 24
Finished Feb 28 04:17:10 PM PST 24
Peak memory 184168 kb
Host smart-2bf1f8f4-384b-48df-8bd7-dab8378889bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325434744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.325434744
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.672566061
Short name T663
Test name
Test status
Simulation time 25417457 ps
CPU time 0.85 seconds
Started Feb 28 04:17:06 PM PST 24
Finished Feb 28 04:17:07 PM PST 24
Peak memory 192464 kb
Host smart-3dc48725-2228-48de-afd8-0b9356f28866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672566061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.672566061
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1243298675
Short name T637
Test name
Test status
Simulation time 57711592 ps
CPU time 3.13 seconds
Started Feb 28 04:17:06 PM PST 24
Finished Feb 28 04:17:09 PM PST 24
Peak memory 199164 kb
Host smart-ca848c7e-c83f-4d2c-ab69-8d02ccb06e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243298675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1243298675
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3133247179
Short name T701
Test name
Test status
Simulation time 309159683 ps
CPU time 2.46 seconds
Started Feb 28 04:17:08 PM PST 24
Finished Feb 28 04:17:10 PM PST 24
Peak memory 198960 kb
Host smart-42b9e590-8139-4207-baaa-8a72a8297432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133247179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3133247179
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.333982462
Short name T728
Test name
Test status
Simulation time 60240930 ps
CPU time 1.54 seconds
Started Feb 28 04:17:26 PM PST 24
Finished Feb 28 04:17:28 PM PST 24
Peak memory 198996 kb
Host smart-4a4c2ea3-8e3a-491c-b88f-3ed45ab651ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333982462 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.333982462
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2769968739
Short name T79
Test name
Test status
Simulation time 12996161 ps
CPU time 0.76 seconds
Started Feb 28 04:16:58 PM PST 24
Finished Feb 28 04:16:59 PM PST 24
Peak memory 194820 kb
Host smart-66065f81-cc7c-44bf-b73f-6aab3e2caf05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769968739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2769968739
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2940008820
Short name T605
Test name
Test status
Simulation time 79298988 ps
CPU time 0.61 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 184144 kb
Host smart-33eaf057-5e4e-462b-ac27-a227decf4346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940008820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2940008820
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3656065663
Short name T627
Test name
Test status
Simulation time 57532527 ps
CPU time 0.81 seconds
Started Feb 28 04:17:23 PM PST 24
Finished Feb 28 04:17:24 PM PST 24
Peak memory 192448 kb
Host smart-9ff7c26c-04ca-4d87-92f0-fd2d007bad81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656065663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3656065663
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3040797048
Short name T696
Test name
Test status
Simulation time 89254029 ps
CPU time 2.48 seconds
Started Feb 28 04:17:29 PM PST 24
Finished Feb 28 04:17:32 PM PST 24
Peak memory 199028 kb
Host smart-6fabe1d2-a134-4328-8f28-fc79def7cf00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040797048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3040797048
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3528862666
Short name T708
Test name
Test status
Simulation time 174614799 ps
CPU time 1.22 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:15 PM PST 24
Peak memory 198360 kb
Host smart-a4ae2b87-256b-4cef-a79b-3281e2722036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528862666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3528862666
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4228429586
Short name T617
Test name
Test status
Simulation time 68790174 ps
CPU time 1.68 seconds
Started Feb 28 04:18:01 PM PST 24
Finished Feb 28 04:18:03 PM PST 24
Peak memory 199056 kb
Host smart-091768c4-1da2-4f61-9eb5-b8af0a3afa11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228429586 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4228429586
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.677320441
Short name T82
Test name
Test status
Simulation time 15828056 ps
CPU time 0.64 seconds
Started Feb 28 04:17:17 PM PST 24
Finished Feb 28 04:17:18 PM PST 24
Peak memory 194952 kb
Host smart-fac370ac-c65b-46d0-939c-245e48edcc3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677320441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.677320441
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1535470831
Short name T633
Test name
Test status
Simulation time 22246046 ps
CPU time 0.64 seconds
Started Feb 28 04:17:13 PM PST 24
Finished Feb 28 04:17:14 PM PST 24
Peak memory 184236 kb
Host smart-fca54a5f-1bd2-466f-bd9b-94529e67b5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535470831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1535470831
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2569361605
Short name T658
Test name
Test status
Simulation time 64344105 ps
CPU time 1.38 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 192604 kb
Host smart-ad333ef6-5840-461b-8bf1-c0e42ea1e829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569361605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2569361605
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3973530096
Short name T716
Test name
Test status
Simulation time 562734554 ps
CPU time 2.85 seconds
Started Feb 28 04:17:14 PM PST 24
Finished Feb 28 04:17:17 PM PST 24
Peak memory 199028 kb
Host smart-f094ffcc-ae5e-4703-9a60-26ac6d6b3356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973530096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3973530096
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2191893630
Short name T139
Test name
Test status
Simulation time 193277480 ps
CPU time 1.12 seconds
Started Feb 28 04:17:11 PM PST 24
Finished Feb 28 04:17:12 PM PST 24
Peak memory 198176 kb
Host smart-0d9e2b66-db0c-4fba-a5fc-4dda63caba91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191893630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2191893630
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.250268900
Short name T720
Test name
Test status
Simulation time 63561896 ps
CPU time 1.71 seconds
Started Feb 28 04:17:11 PM PST 24
Finished Feb 28 04:17:13 PM PST 24
Peak memory 199024 kb
Host smart-c9edda65-1874-4f1b-8d50-5da4fdf26231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250268900 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.250268900
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2721476567
Short name T94
Test name
Test status
Simulation time 12387338 ps
CPU time 0.65 seconds
Started Feb 28 04:17:02 PM PST 24
Finished Feb 28 04:17:03 PM PST 24
Peak memory 194696 kb
Host smart-76ae0550-0b11-4c08-a96e-68d188615c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721476567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2721476567
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2540801796
Short name T666
Test name
Test status
Simulation time 20120066 ps
CPU time 0.58 seconds
Started Feb 28 04:17:18 PM PST 24
Finished Feb 28 04:17:19 PM PST 24
Peak memory 184040 kb
Host smart-66d952f9-2671-4b74-8d5b-41e672266a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540801796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2540801796
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2349554140
Short name T718
Test name
Test status
Simulation time 36987919 ps
CPU time 0.98 seconds
Started Feb 28 04:17:39 PM PST 24
Finished Feb 28 04:17:40 PM PST 24
Peak memory 192632 kb
Host smart-35980c56-148d-4375-8abf-0141eb6dfb8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349554140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2349554140
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2038552108
Short name T626
Test name
Test status
Simulation time 129185593 ps
CPU time 1.91 seconds
Started Feb 28 04:18:02 PM PST 24
Finished Feb 28 04:18:04 PM PST 24
Peak memory 199068 kb
Host smart-fb3fac2b-df27-437f-8c8c-51f1839bd75d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038552108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2038552108
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2500541392
Short name T343
Test name
Test status
Simulation time 17833397 ps
CPU time 0.6 seconds
Started Feb 28 04:42:41 PM PST 24
Finished Feb 28 04:42:42 PM PST 24
Peak memory 195108 kb
Host smart-241192d8-6dac-4b45-a662-5643304d164e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500541392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2500541392
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.790029499
Short name T579
Test name
Test status
Simulation time 1194412130 ps
CPU time 17.23 seconds
Started Feb 28 04:42:38 PM PST 24
Finished Feb 28 04:42:56 PM PST 24
Peak memory 229660 kb
Host smart-f34598e6-70a1-45c7-9f15-2e5180fb23a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790029499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.790029499
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.295565387
Short name T266
Test name
Test status
Simulation time 8605604049 ps
CPU time 42.81 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:43:23 PM PST 24
Peak memory 199508 kb
Host smart-c2a90b92-ce71-48e1-ba98-f202a5f57ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295565387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.295565387
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2358141634
Short name T474
Test name
Test status
Simulation time 1232543491 ps
CPU time 16.5 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:42:57 PM PST 24
Peak memory 199464 kb
Host smart-ba7d1227-f176-4ba2-ac24-58171a5ccb6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358141634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2358141634
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2305654946
Short name T447
Test name
Test status
Simulation time 37185600168 ps
CPU time 150.43 seconds
Started Feb 28 04:42:44 PM PST 24
Finished Feb 28 04:45:15 PM PST 24
Peak memory 199480 kb
Host smart-5be0c13c-7043-4f57-a0d2-2c55d851fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305654946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2305654946
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3773682006
Short name T532
Test name
Test status
Simulation time 4237660712 ps
CPU time 77.81 seconds
Started Feb 28 04:42:35 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 199520 kb
Host smart-739769c7-5d34-48bc-8804-c5e85902759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773682006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3773682006
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3081048944
Short name T25
Test name
Test status
Simulation time 258266632 ps
CPU time 0.89 seconds
Started Feb 28 04:42:41 PM PST 24
Finished Feb 28 04:42:42 PM PST 24
Peak memory 216536 kb
Host smart-2f5754b6-dd34-4fce-a3a4-69f99879d1f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081048944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3081048944
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1991608837
Short name T417
Test name
Test status
Simulation time 385726411 ps
CPU time 2.41 seconds
Started Feb 28 04:42:36 PM PST 24
Finished Feb 28 04:42:38 PM PST 24
Peak memory 199400 kb
Host smart-26ec9aa5-f988-40c2-b9d7-cf275668bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991608837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1991608837
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.885605567
Short name T390
Test name
Test status
Simulation time 70352781 ps
CPU time 1.12 seconds
Started Feb 28 04:42:36 PM PST 24
Finished Feb 28 04:42:37 PM PST 24
Peak memory 198152 kb
Host smart-5d263e3d-b659-4129-8597-b2a0da2f0ff4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885605567 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.885605567
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3678497502
Short name T308
Test name
Test status
Simulation time 170993628433 ps
CPU time 509.03 seconds
Started Feb 28 04:42:37 PM PST 24
Finished Feb 28 04:51:06 PM PST 24
Peak memory 199360 kb
Host smart-8f27ea5e-d8b2-4d92-9c34-2a68fde36819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678497502 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.3678497502
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2873080108
Short name T548
Test name
Test status
Simulation time 326345146 ps
CPU time 16.96 seconds
Started Feb 28 04:42:38 PM PST 24
Finished Feb 28 04:42:55 PM PST 24
Peak memory 199456 kb
Host smart-d1172a4e-6ad3-4716-aa0d-5077a6f292e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873080108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2873080108
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.749854816
Short name T540
Test name
Test status
Simulation time 3180062978 ps
CPU time 26.23 seconds
Started Feb 28 04:42:42 PM PST 24
Finished Feb 28 04:43:08 PM PST 24
Peak memory 215844 kb
Host smart-bc5f8e0d-8fb2-49e0-a4a6-f69727f5134a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749854816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.749854816
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2686594218
Short name T279
Test name
Test status
Simulation time 68438019 ps
CPU time 1.59 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 04:42:47 PM PST 24
Peak memory 199284 kb
Host smart-143a87d4-2a1c-4948-ac25-f648f0afd2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686594218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2686594218
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1809900914
Short name T414
Test name
Test status
Simulation time 1631616271 ps
CPU time 87.36 seconds
Started Feb 28 04:42:42 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 199476 kb
Host smart-4c3f17e5-eaa8-4742-86bf-14567c733235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809900914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1809900914
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3673803611
Short name T583
Test name
Test status
Simulation time 7767972102 ps
CPU time 103.46 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 04:44:29 PM PST 24
Peak memory 199572 kb
Host smart-6afdcaab-da79-42aa-b435-e583e23c60c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673803611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3673803611
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.362351497
Short name T254
Test name
Test status
Simulation time 5413592559 ps
CPU time 82.7 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:44:03 PM PST 24
Peak memory 199484 kb
Host smart-25f9c894-6d7f-4ef9-92a9-9cfcfcfbf6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362351497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.362351497
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2692937189
Short name T460
Test name
Test status
Simulation time 21703239 ps
CPU time 0.81 seconds
Started Feb 28 04:42:43 PM PST 24
Finished Feb 28 04:42:44 PM PST 24
Peak memory 196464 kb
Host smart-cbe44244-a396-466c-8cf3-fec6bc08969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692937189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2692937189
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2158199830
Short name T318
Test name
Test status
Simulation time 60821847 ps
CPU time 1.38 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:42:41 PM PST 24
Peak memory 199432 kb
Host smart-73516704-5466-456e-8ffb-e3dcc3eda044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158199830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2158199830
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.839491890
Short name T574
Test name
Test status
Simulation time 44932583 ps
CPU time 1.15 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:42:42 PM PST 24
Peak memory 198304 kb
Host smart-0079e52c-6b3b-4631-9aae-27947289be4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839491890 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.839491890
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.942790507
Short name T586
Test name
Test status
Simulation time 48772024530 ps
CPU time 409.14 seconds
Started Feb 28 04:42:46 PM PST 24
Finished Feb 28 04:49:36 PM PST 24
Peak memory 199504 kb
Host smart-f73849fc-f87e-41ad-b781-67b3300c7bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942790507 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_sha_vectors.942790507
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3873727183
Short name T407
Test name
Test status
Simulation time 5424083271 ps
CPU time 17.84 seconds
Started Feb 28 04:42:40 PM PST 24
Finished Feb 28 04:42:58 PM PST 24
Peak memory 199536 kb
Host smart-ed833fea-57d4-4e36-b0a7-3d9143cb75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873727183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3873727183
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1486003311
Short name T159
Test name
Test status
Simulation time 14087481 ps
CPU time 0.59 seconds
Started Feb 28 04:43:19 PM PST 24
Finished Feb 28 04:43:20 PM PST 24
Peak memory 193812 kb
Host smart-e8cc4980-3358-4c4f-bdfa-c6907a2a4c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486003311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1486003311
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1224862532
Short name T505
Test name
Test status
Simulation time 799636156 ps
CPU time 6.06 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:43:26 PM PST 24
Peak memory 199384 kb
Host smart-519a92b2-64ed-4064-baa6-7d62bd273461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224862532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1224862532
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.551005991
Short name T562
Test name
Test status
Simulation time 679292527 ps
CPU time 32.97 seconds
Started Feb 28 04:43:19 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 199472 kb
Host smart-87d4691f-e9d4-49c0-939e-ed380db64f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551005991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.551005991
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3861140216
Short name T425
Test name
Test status
Simulation time 45537859 ps
CPU time 2.47 seconds
Started Feb 28 04:43:13 PM PST 24
Finished Feb 28 04:43:16 PM PST 24
Peak memory 199400 kb
Host smart-373d590d-c506-4fb7-a0d1-6f5ba903623f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861140216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3861140216
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1345602248
Short name T373
Test name
Test status
Simulation time 4108844189 ps
CPU time 56.18 seconds
Started Feb 28 04:43:13 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 199476 kb
Host smart-ee2426eb-0b1c-43f3-9f7c-bf1f6bf957a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345602248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1345602248
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3835726559
Short name T292
Test name
Test status
Simulation time 4320995263 ps
CPU time 15.32 seconds
Started Feb 28 04:43:14 PM PST 24
Finished Feb 28 04:43:30 PM PST 24
Peak memory 199520 kb
Host smart-92f0f0c4-d3dd-4019-bccd-261d6449c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835726559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3835726559
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2179975275
Short name T535
Test name
Test status
Simulation time 62571764 ps
CPU time 1.53 seconds
Started Feb 28 04:43:14 PM PST 24
Finished Feb 28 04:43:16 PM PST 24
Peak memory 199404 kb
Host smart-d3714985-dff8-4726-947e-92d41930d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179975275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2179975275
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3517042865
Short name T508
Test name
Test status
Simulation time 757578228661 ps
CPU time 2519.06 seconds
Started Feb 28 04:43:19 PM PST 24
Finished Feb 28 05:25:19 PM PST 24
Peak memory 232224 kb
Host smart-475fe371-c5a5-4ba2-835b-bb66523ab621
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517042865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3517042865
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1588328215
Short name T507
Test name
Test status
Simulation time 204202566 ps
CPU time 1.13 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:43:21 PM PST 24
Peak memory 198464 kb
Host smart-bb12a87a-73b4-4079-a6d1-a9f2872a4fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588328215 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1588328215
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1980127550
Short name T429
Test name
Test status
Simulation time 10666825739 ps
CPU time 449.18 seconds
Started Feb 28 04:43:13 PM PST 24
Finished Feb 28 04:50:42 PM PST 24
Peak memory 199524 kb
Host smart-29ea222b-17ef-43ba-8181-7707290ef714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980127550 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.1980127550
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.11851008
Short name T445
Test name
Test status
Simulation time 2149365124 ps
CPU time 78.15 seconds
Started Feb 28 04:43:11 PM PST 24
Finished Feb 28 04:44:31 PM PST 24
Peak memory 199488 kb
Host smart-77a51d69-3bac-4044-afdb-4b3a53d3ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11851008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.11851008
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1682669934
Short name T537
Test name
Test status
Simulation time 23682281 ps
CPU time 0.64 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:43:21 PM PST 24
Peak memory 193980 kb
Host smart-35f948e4-3345-4064-9d27-a5a73a790703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682669934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1682669934
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2447624908
Short name T522
Test name
Test status
Simulation time 656026860 ps
CPU time 21.45 seconds
Started Feb 28 04:43:14 PM PST 24
Finished Feb 28 04:43:36 PM PST 24
Peak memory 215816 kb
Host smart-f0920085-ccdc-4980-8115-9b4c36129d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447624908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2447624908
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3663506981
Short name T393
Test name
Test status
Simulation time 1952303589 ps
CPU time 9.24 seconds
Started Feb 28 04:43:16 PM PST 24
Finished Feb 28 04:43:26 PM PST 24
Peak memory 199452 kb
Host smart-676a7f6c-d5eb-47ca-802a-54a48d93a228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663506981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3663506981
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.15507022
Short name T521
Test name
Test status
Simulation time 1280556249 ps
CPU time 68.61 seconds
Started Feb 28 04:43:15 PM PST 24
Finished Feb 28 04:44:24 PM PST 24
Peak memory 199456 kb
Host smart-9df1aa16-4caf-4b05-b425-843c8ed8041a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15507022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.15507022
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1948390989
Short name T281
Test name
Test status
Simulation time 24441963181 ps
CPU time 101.2 seconds
Started Feb 28 04:43:16 PM PST 24
Finished Feb 28 04:44:58 PM PST 24
Peak memory 199516 kb
Host smart-29d2ad19-eb7e-41ea-bfb0-ccc4d7dab248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948390989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1948390989
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1433561832
Short name T244
Test name
Test status
Simulation time 22562295 ps
CPU time 1.04 seconds
Started Feb 28 04:43:18 PM PST 24
Finished Feb 28 04:43:20 PM PST 24
Peak memory 199112 kb
Host smart-5d5d3633-9a76-470e-8914-0458bc96b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433561832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1433561832
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.962570095
Short name T345
Test name
Test status
Simulation time 196826950 ps
CPU time 2.65 seconds
Started Feb 28 04:43:14 PM PST 24
Finished Feb 28 04:43:16 PM PST 24
Peak memory 199400 kb
Host smart-dcdd1b26-85f8-468e-809f-b86422893971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962570095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.962570095
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2397825671
Short name T530
Test name
Test status
Simulation time 47965609237 ps
CPU time 270.92 seconds
Started Feb 28 04:43:18 PM PST 24
Finished Feb 28 04:47:49 PM PST 24
Peak memory 199528 kb
Host smart-86c89cd4-c9ca-4aba-826f-0e8f78e339b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397825671 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2397825671
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1589613793
Short name T207
Test name
Test status
Simulation time 82472347 ps
CPU time 1 seconds
Started Feb 28 04:43:17 PM PST 24
Finished Feb 28 04:43:18 PM PST 24
Peak memory 197272 kb
Host smart-6ba22115-31e1-4cf8-ad5a-5bf3ed39c4a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589613793 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1589613793
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2474849194
Short name T309
Test name
Test status
Simulation time 12230462752 ps
CPU time 323.67 seconds
Started Feb 28 04:43:14 PM PST 24
Finished Feb 28 04:48:38 PM PST 24
Peak memory 199380 kb
Host smart-1c757827-f018-444d-8d7b-1b3dd9c17694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474849194 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2474849194
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2835948332
Short name T183
Test name
Test status
Simulation time 2496035319 ps
CPU time 60.04 seconds
Started Feb 28 04:43:16 PM PST 24
Finished Feb 28 04:44:17 PM PST 24
Peak memory 199444 kb
Host smart-83fe3a62-cf97-46f6-af3b-6f1251a5d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835948332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2835948332
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.1527562583
Short name T20
Test name
Test status
Simulation time 4808225234 ps
CPU time 244.88 seconds
Started Feb 28 04:45:31 PM PST 24
Finished Feb 28 04:49:36 PM PST 24
Peak memory 216044 kb
Host smart-623e6e90-c110-437b-82d3-55b37de98586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527562583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.1527562583
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3617036662
Short name T559
Test name
Test status
Simulation time 41775974 ps
CPU time 0.59 seconds
Started Feb 28 04:43:24 PM PST 24
Finished Feb 28 04:43:25 PM PST 24
Peak memory 193660 kb
Host smart-1569e71e-8813-4bcc-910c-3bab97a7161f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617036662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3617036662
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.401359033
Short name T370
Test name
Test status
Simulation time 1103632928 ps
CPU time 40.7 seconds
Started Feb 28 04:43:21 PM PST 24
Finished Feb 28 04:44:02 PM PST 24
Peak memory 230588 kb
Host smart-abee81ae-3334-4786-9acc-dd535894e4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401359033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.401359033
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3699093802
Short name T267
Test name
Test status
Simulation time 51005175 ps
CPU time 2.61 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:43:23 PM PST 24
Peak memory 199452 kb
Host smart-e87946b7-f5ac-4d03-87dd-a59b2b546a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699093802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3699093802
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2458177853
Short name T327
Test name
Test status
Simulation time 6601178382 ps
CPU time 109.8 seconds
Started Feb 28 04:43:20 PM PST 24
Finished Feb 28 04:45:10 PM PST 24
Peak memory 199520 kb
Host smart-2f981075-df98-4f51-ad8b-0149f686dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458177853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2458177853
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1284255126
Short name T192
Test name
Test status
Simulation time 6649377707 ps
CPU time 92.34 seconds
Started Feb 28 04:43:19 PM PST 24
Finished Feb 28 04:44:52 PM PST 24
Peak memory 199480 kb
Host smart-bb0fb0b0-c2ea-412d-beb6-99a37e2bf7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284255126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1284255126
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3559615174
Short name T564
Test name
Test status
Simulation time 316031854 ps
CPU time 3.17 seconds
Started Feb 28 04:43:21 PM PST 24
Finished Feb 28 04:43:25 PM PST 24
Peak memory 199544 kb
Host smart-2badbe82-9090-4286-9c43-737079c8f0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559615174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3559615174
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.497482453
Short name T247
Test name
Test status
Simulation time 9507243917 ps
CPU time 63.05 seconds
Started Feb 28 04:43:22 PM PST 24
Finished Feb 28 04:44:25 PM PST 24
Peak memory 231568 kb
Host smart-6cf7864a-1d1a-43a2-b6a2-dc7404c7415f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497482453 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.497482453
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1200029260
Short name T236
Test name
Test status
Simulation time 66841503 ps
CPU time 1.07 seconds
Started Feb 28 04:43:18 PM PST 24
Finished Feb 28 04:43:19 PM PST 24
Peak memory 198384 kb
Host smart-3f40505c-7d8f-49da-8045-76f374ba639e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200029260 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1200029260
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3592929674
Short name T321
Test name
Test status
Simulation time 7898002245 ps
CPU time 450.88 seconds
Started Feb 28 04:43:24 PM PST 24
Finished Feb 28 04:50:55 PM PST 24
Peak memory 199592 kb
Host smart-a8b19a18-6dbb-4a37-a7ce-c7d6089fdcf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592929674 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3592929674
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3959422754
Short name T157
Test name
Test status
Simulation time 4184736602 ps
CPU time 78.45 seconds
Started Feb 28 04:43:21 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199496 kb
Host smart-f6569181-4858-4bca-b2a5-827f6667dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959422754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3959422754
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1987951393
Short name T14
Test name
Test status
Simulation time 47976721 ps
CPU time 0.61 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:43:27 PM PST 24
Peak memory 193848 kb
Host smart-5754a17b-7114-47af-bd7c-600bba623e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987951393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1987951393
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1899450787
Short name T470
Test name
Test status
Simulation time 352391769 ps
CPU time 10.59 seconds
Started Feb 28 04:43:24 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 199348 kb
Host smart-afed25e4-7891-4262-80ca-bdf1726c46aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899450787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1899450787
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2529813240
Short name T341
Test name
Test status
Simulation time 70919639762 ps
CPU time 51.02 seconds
Started Feb 28 04:43:23 PM PST 24
Finished Feb 28 04:44:14 PM PST 24
Peak memory 199480 kb
Host smart-53c0c272-76e5-43ef-9313-b493bfa72480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529813240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2529813240
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3471604934
Short name T475
Test name
Test status
Simulation time 1534625770 ps
CPU time 53.68 seconds
Started Feb 28 04:43:21 PM PST 24
Finished Feb 28 04:44:15 PM PST 24
Peak memory 199480 kb
Host smart-a9aaa02e-da5b-4ab5-b9d9-fad03d0ae4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471604934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3471604934
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2374751233
Short name T570
Test name
Test status
Simulation time 1006197513 ps
CPU time 26.03 seconds
Started Feb 28 04:43:23 PM PST 24
Finished Feb 28 04:43:49 PM PST 24
Peak memory 199432 kb
Host smart-c1575a01-1dac-44d9-9326-1a75363642e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374751233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2374751233
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1979249531
Short name T21
Test name
Test status
Simulation time 1092249395 ps
CPU time 2.62 seconds
Started Feb 28 04:43:23 PM PST 24
Finished Feb 28 04:43:26 PM PST 24
Peak memory 199344 kb
Host smart-fe8a7f0a-2bd8-42e1-8dbc-93777a8c6b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979249531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1979249531
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1544723610
Short name T146
Test name
Test status
Simulation time 41243251 ps
CPU time 0.96 seconds
Started Feb 28 04:43:25 PM PST 24
Finished Feb 28 04:43:26 PM PST 24
Peak memory 196772 kb
Host smart-aff01d8e-3115-4508-86ff-df90887b94b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544723610 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1544723610
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3886207285
Short name T151
Test name
Test status
Simulation time 117422021169 ps
CPU time 400.12 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:50:07 PM PST 24
Peak memory 199512 kb
Host smart-8d18c162-dcf9-406a-af75-e7fb306f60b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886207285 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.3886207285
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4190497801
Short name T253
Test name
Test status
Simulation time 5568586071 ps
CPU time 39.81 seconds
Started Feb 28 04:43:27 PM PST 24
Finished Feb 28 04:44:07 PM PST 24
Peak memory 199520 kb
Host smart-1766b96b-d4be-4762-ba47-b6b5a6c7e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190497801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4190497801
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3683961293
Short name T201
Test name
Test status
Simulation time 116862778 ps
CPU time 0.61 seconds
Started Feb 28 04:43:30 PM PST 24
Finished Feb 28 04:43:31 PM PST 24
Peak memory 193828 kb
Host smart-25f28163-16f5-46e2-a2e8-4ed252187491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683961293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3683961293
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1194122413
Short name T400
Test name
Test status
Simulation time 130495733 ps
CPU time 3.04 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:43:30 PM PST 24
Peak memory 199536 kb
Host smart-eafd9fd4-98a5-4357-8100-b897245ca6f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194122413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1194122413
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2095947407
Short name T232
Test name
Test status
Simulation time 1079169266 ps
CPU time 2.83 seconds
Started Feb 28 04:43:25 PM PST 24
Finished Feb 28 04:43:28 PM PST 24
Peak memory 199456 kb
Host smart-ed91bff0-cc33-4e7f-9922-8c3b9e49344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095947407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2095947407
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1221849392
Short name T105
Test name
Test status
Simulation time 846133080 ps
CPU time 44.23 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199380 kb
Host smart-07b4a433-66af-4b5d-b19c-c938a86941a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221849392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1221849392
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.59464216
Short name T147
Test name
Test status
Simulation time 11279739 ps
CPU time 0.58 seconds
Started Feb 28 04:43:35 PM PST 24
Finished Feb 28 04:43:36 PM PST 24
Peak memory 193824 kb
Host smart-1b839538-b1d3-401a-94f1-9b0c8807707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59464216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.59464216
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.4058965716
Short name T31
Test name
Test status
Simulation time 1487565075 ps
CPU time 18.3 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:43:45 PM PST 24
Peak memory 199404 kb
Host smart-ffe90e25-3143-489c-964b-5164e3f32476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058965716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4058965716
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4078668475
Short name T544
Test name
Test status
Simulation time 248134525 ps
CPU time 2.98 seconds
Started Feb 28 04:43:27 PM PST 24
Finished Feb 28 04:43:30 PM PST 24
Peak memory 199296 kb
Host smart-e3910441-87d6-4da2-b3f4-8f1dbe743d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078668475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4078668475
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.730637104
Short name T472
Test name
Test status
Simulation time 69958547 ps
CPU time 1.2 seconds
Started Feb 28 04:43:27 PM PST 24
Finished Feb 28 04:43:29 PM PST 24
Peak memory 198244 kb
Host smart-063b9aa8-2cf6-4b7c-b46e-ab63e4fbefb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730637104 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.730637104
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1025450618
Short name T187
Test name
Test status
Simulation time 32035205646 ps
CPU time 412 seconds
Started Feb 28 04:43:35 PM PST 24
Finished Feb 28 04:50:27 PM PST 24
Peak memory 199392 kb
Host smart-61c26019-3a07-4be0-8068-7668fca0b708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025450618 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.1025450618
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3358647487
Short name T500
Test name
Test status
Simulation time 4527425233 ps
CPU time 74.65 seconds
Started Feb 28 04:43:26 PM PST 24
Finished Feb 28 04:44:41 PM PST 24
Peak memory 199520 kb
Host smart-39cf296b-5fe1-4f34-a8ad-f26e979cae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358647487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3358647487
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3124759564
Short name T471
Test name
Test status
Simulation time 12739535 ps
CPU time 0.56 seconds
Started Feb 28 04:43:31 PM PST 24
Finished Feb 28 04:43:32 PM PST 24
Peak memory 193812 kb
Host smart-5dfa641a-eaaa-4089-827a-53a2bc665ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124759564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3124759564
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.674799860
Short name T2
Test name
Test status
Simulation time 169723532 ps
CPU time 5.38 seconds
Started Feb 28 04:43:29 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 215456 kb
Host smart-e640e55a-5007-4abf-a99f-c622f5005342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674799860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.674799860
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3650389101
Short name T506
Test name
Test status
Simulation time 817126890 ps
CPU time 8.16 seconds
Started Feb 28 04:43:31 PM PST 24
Finished Feb 28 04:43:39 PM PST 24
Peak memory 199316 kb
Host smart-122545a5-7d45-4a6e-b676-85b98d523f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650389101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3650389101
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.553012317
Short name T45
Test name
Test status
Simulation time 544604113 ps
CPU time 29.5 seconds
Started Feb 28 04:43:31 PM PST 24
Finished Feb 28 04:44:01 PM PST 24
Peak memory 199464 kb
Host smart-28701c69-9d40-4568-87c2-7d696702e17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553012317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.553012317
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1510371660
Short name T273
Test name
Test status
Simulation time 8828632738 ps
CPU time 115.95 seconds
Started Feb 28 04:43:34 PM PST 24
Finished Feb 28 04:45:31 PM PST 24
Peak memory 199404 kb
Host smart-f8329bf9-b20d-4f2a-afe5-304a2c8c99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510371660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1510371660
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1585824318
Short name T44
Test name
Test status
Simulation time 8594316061 ps
CPU time 76.17 seconds
Started Feb 28 04:43:28 PM PST 24
Finished Feb 28 04:44:44 PM PST 24
Peak memory 199552 kb
Host smart-58275eb6-ec6a-4b35-a28c-ca6c7fc19757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585824318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1585824318
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3403499387
Short name T459
Test name
Test status
Simulation time 282179636 ps
CPU time 3.33 seconds
Started Feb 28 04:43:29 PM PST 24
Finished Feb 28 04:43:32 PM PST 24
Peak memory 199420 kb
Host smart-5e5f1552-efd9-48d2-9f05-9366e4f632e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403499387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3403499387
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.285263086
Short name T421
Test name
Test status
Simulation time 461124112 ps
CPU time 6.64 seconds
Started Feb 28 04:43:28 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 199476 kb
Host smart-14e91bb6-893e-4a27-9cf2-b29d3a650414
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285263086 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.285263086
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.610831035
Short name T338
Test name
Test status
Simulation time 66863975 ps
CPU time 1.17 seconds
Started Feb 28 04:43:29 PM PST 24
Finished Feb 28 04:43:31 PM PST 24
Peak memory 198200 kb
Host smart-82198660-a3af-4f6a-9ae4-3c571eacb3fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610831035 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.610831035
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1688995486
Short name T340
Test name
Test status
Simulation time 6708883130 ps
CPU time 22.52 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 199476 kb
Host smart-aea261dd-ca7d-40d4-89c3-e48449875a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688995486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1688995486
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.318128439
Short name T62
Test name
Test status
Simulation time 49198444932 ps
CPU time 369.81 seconds
Started Feb 28 04:45:42 PM PST 24
Finished Feb 28 04:51:52 PM PST 24
Peak memory 207840 kb
Host smart-bc8f7f5a-ef1f-4018-917c-dd959c88e5b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318128439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.318128439
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3190197045
Short name T420
Test name
Test status
Simulation time 29636326 ps
CPU time 0.57 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:43:34 PM PST 24
Peak memory 193836 kb
Host smart-6c6454b5-739a-4d9b-9f35-39631d26ba8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190197045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3190197045
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2833313080
Short name T549
Test name
Test status
Simulation time 1323646043 ps
CPU time 30.52 seconds
Started Feb 28 04:43:31 PM PST 24
Finished Feb 28 04:44:02 PM PST 24
Peak memory 221076 kb
Host smart-c6edba87-9798-4eab-998d-198c4e86a70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833313080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2833313080
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2828298724
Short name T499
Test name
Test status
Simulation time 4661144556 ps
CPU time 22.24 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 199500 kb
Host smart-2a322677-6b70-4a24-a0d3-57ad509eb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828298724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2828298724
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2950209480
Short name T251
Test name
Test status
Simulation time 6513109064 ps
CPU time 85.8 seconds
Started Feb 28 04:43:35 PM PST 24
Finished Feb 28 04:45:01 PM PST 24
Peak memory 199480 kb
Host smart-579c1645-8034-425f-a086-5a1011ffe312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950209480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2950209480
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2287966117
Short name T560
Test name
Test status
Simulation time 3394018897 ps
CPU time 56.11 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:44:30 PM PST 24
Peak memory 199500 kb
Host smart-a8503c6b-b87b-4d19-8c4b-3f942b393f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287966117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2287966117
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2999655291
Short name T596
Test name
Test status
Simulation time 4460268954 ps
CPU time 60.25 seconds
Started Feb 28 04:43:35 PM PST 24
Finished Feb 28 04:44:36 PM PST 24
Peak memory 199516 kb
Host smart-aee84ea0-358e-405b-90fc-31afe0ab59ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999655291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2999655291
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.622899951
Short name T387
Test name
Test status
Simulation time 269743830 ps
CPU time 1.84 seconds
Started Feb 28 04:43:29 PM PST 24
Finished Feb 28 04:43:31 PM PST 24
Peak memory 199432 kb
Host smart-1d3e8c6e-604f-45d6-b342-8421474cbddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622899951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.622899951
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3430794927
Short name T55
Test name
Test status
Simulation time 226002768330 ps
CPU time 2096.49 seconds
Started Feb 28 04:43:34 PM PST 24
Finished Feb 28 05:18:31 PM PST 24
Peak memory 213396 kb
Host smart-f45f5f54-c6e6-412a-b839-03e5d04a1b24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430794927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3430794927
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1874124139
Short name T149
Test name
Test status
Simulation time 53312673 ps
CPU time 1.14 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 198496 kb
Host smart-c21f2228-a711-4d94-b865-8f7fcf2c95ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874124139 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1874124139
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3881223297
Short name T398
Test name
Test status
Simulation time 16663859272 ps
CPU time 421.7 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:50:35 PM PST 24
Peak memory 199440 kb
Host smart-fa6ed760-d69d-4432-a318-b21dd6b1f573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881223297 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.3881223297
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3788414596
Short name T519
Test name
Test status
Simulation time 1850079523 ps
CPU time 9.01 seconds
Started Feb 28 04:43:34 PM PST 24
Finished Feb 28 04:43:44 PM PST 24
Peak memory 199440 kb
Host smart-5346e172-426a-4fc7-9d07-136e413e6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788414596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3788414596
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.2487450013
Short name T104
Test name
Test status
Simulation time 63527316687 ps
CPU time 2118.71 seconds
Started Feb 28 04:45:40 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 256912 kb
Host smart-77426eed-e419-45d2-8b83-ac7f5838c94d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487450013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.2487450013
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.2622258111
Short name T61
Test name
Test status
Simulation time 24371827655 ps
CPU time 452.67 seconds
Started Feb 28 04:45:45 PM PST 24
Finished Feb 28 04:53:18 PM PST 24
Peak memory 235512 kb
Host smart-e252558c-7f45-4ce9-9059-5f01e8150c13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622258111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.2622258111
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2477937570
Short name T382
Test name
Test status
Simulation time 14454563 ps
CPU time 0.57 seconds
Started Feb 28 04:43:40 PM PST 24
Finished Feb 28 04:43:40 PM PST 24
Peak memory 193672 kb
Host smart-6936f4b6-09ea-47f9-8044-c1ba3ebaa97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477937570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2477937570
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4055261583
Short name T557
Test name
Test status
Simulation time 250161392 ps
CPU time 7.56 seconds
Started Feb 28 04:43:32 PM PST 24
Finished Feb 28 04:43:40 PM PST 24
Peak memory 199460 kb
Host smart-1b8d66a1-94af-4198-b0cb-8a53a18bce60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055261583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4055261583
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3414487748
Short name T302
Test name
Test status
Simulation time 4684621536 ps
CPU time 45.57 seconds
Started Feb 28 04:43:32 PM PST 24
Finished Feb 28 04:44:18 PM PST 24
Peak memory 199504 kb
Host smart-ef1b3345-7129-45e8-9d61-d93440882e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414487748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3414487748
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.36302688
Short name T568
Test name
Test status
Simulation time 44871243651 ps
CPU time 148.52 seconds
Started Feb 28 04:43:37 PM PST 24
Finished Feb 28 04:46:06 PM PST 24
Peak memory 199556 kb
Host smart-c71f955d-6687-45b8-a37b-f01f10d3b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36302688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.36302688
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2021379295
Short name T528
Test name
Test status
Simulation time 5189077066 ps
CPU time 18.3 seconds
Started Feb 28 04:43:33 PM PST 24
Finished Feb 28 04:43:52 PM PST 24
Peak memory 199464 kb
Host smart-0a136734-9ee9-40e5-9c67-0c65fabdba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021379295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2021379295
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3054629852
Short name T395
Test name
Test status
Simulation time 116947071 ps
CPU time 1.94 seconds
Started Feb 28 04:43:32 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 199244 kb
Host smart-a4eb2b41-6652-40e0-803e-61f97c85df11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054629852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3054629852
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3518459750
Short name T307
Test name
Test status
Simulation time 12988697009 ps
CPU time 668.39 seconds
Started Feb 28 04:43:37 PM PST 24
Finished Feb 28 04:54:46 PM PST 24
Peak memory 199560 kb
Host smart-7943bea9-2e1f-481d-ac97-2f08af19ab65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518459750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3518459750
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2549988195
Short name T512
Test name
Test status
Simulation time 51123942 ps
CPU time 0.93 seconds
Started Feb 28 04:43:37 PM PST 24
Finished Feb 28 04:43:38 PM PST 24
Peak memory 196960 kb
Host smart-1c0aa25c-dc1c-4abc-989d-58c6472bab68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549988195 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2549988195
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.478774092
Short name T148
Test name
Test status
Simulation time 35907981067 ps
CPU time 428.33 seconds
Started Feb 28 04:43:35 PM PST 24
Finished Feb 28 04:50:44 PM PST 24
Peak memory 199404 kb
Host smart-aa430fe8-d61b-4cd0-874b-8decee146039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478774092 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_sha_vectors.478774092
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2710816033
Short name T358
Test name
Test status
Simulation time 7938209434 ps
CPU time 45.04 seconds
Started Feb 28 04:43:37 PM PST 24
Finished Feb 28 04:44:22 PM PST 24
Peak memory 199456 kb
Host smart-b3ff44fb-ff08-4342-ae5e-e1de76fd0a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710816033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2710816033
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.1268885976
Short name T38
Test name
Test status
Simulation time 89723893490 ps
CPU time 3524.58 seconds
Started Feb 28 04:45:48 PM PST 24
Finished Feb 28 05:44:34 PM PST 24
Peak memory 264848 kb
Host smart-982941ad-c5df-4a89-b7be-c19544ac0c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268885976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.1268885976
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3477465592
Short name T406
Test name
Test status
Simulation time 21109423 ps
CPU time 0.58 seconds
Started Feb 28 04:43:40 PM PST 24
Finished Feb 28 04:43:41 PM PST 24
Peak memory 193776 kb
Host smart-7958f56a-2bb8-4806-8326-20d61577dafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477465592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3477465592
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.58412311
Short name T520
Test name
Test status
Simulation time 1494981894 ps
CPU time 52.62 seconds
Started Feb 28 04:43:38 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 232188 kb
Host smart-a074fb1c-4e11-4e39-af6c-0acbc4919d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58412311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.58412311
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1903761003
Short name T462
Test name
Test status
Simulation time 5297558751 ps
CPU time 56.11 seconds
Started Feb 28 04:43:44 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199496 kb
Host smart-301019d6-c6d6-4ec5-b6fd-30a1c583d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903761003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1903761003
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3926144490
Short name T534
Test name
Test status
Simulation time 1228278197 ps
CPU time 60.05 seconds
Started Feb 28 04:43:38 PM PST 24
Finished Feb 28 04:44:39 PM PST 24
Peak memory 199376 kb
Host smart-ba03067c-c6dc-42ec-be41-6d474a68a8db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926144490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3926144490
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.116129236
Short name T573
Test name
Test status
Simulation time 5867385285 ps
CPU time 99.72 seconds
Started Feb 28 04:43:41 PM PST 24
Finished Feb 28 04:45:20 PM PST 24
Peak memory 199512 kb
Host smart-62f17da6-5bd3-49ed-8f20-32c67d7f2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116129236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.116129236
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1131071099
Short name T483
Test name
Test status
Simulation time 4281374147 ps
CPU time 61.03 seconds
Started Feb 28 04:43:40 PM PST 24
Finished Feb 28 04:44:42 PM PST 24
Peak memory 199524 kb
Host smart-89435179-0d3a-4385-9afe-05cdec4a8fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131071099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1131071099
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2411402804
Short name T319
Test name
Test status
Simulation time 329415452 ps
CPU time 1.47 seconds
Started Feb 28 04:43:38 PM PST 24
Finished Feb 28 04:43:40 PM PST 24
Peak memory 199188 kb
Host smart-c8581bd4-807e-4ed2-982b-43be7f12b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411402804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2411402804
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.151470821
Short name T435
Test name
Test status
Simulation time 9200230428 ps
CPU time 350.79 seconds
Started Feb 28 04:43:39 PM PST 24
Finished Feb 28 04:49:30 PM PST 24
Peak memory 230236 kb
Host smart-240ce63e-7946-4e31-bda9-0921bb6cb57f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151470821 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.151470821
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2224036209
Short name T214
Test name
Test status
Simulation time 56499836 ps
CPU time 1.26 seconds
Started Feb 28 04:43:39 PM PST 24
Finished Feb 28 04:43:41 PM PST 24
Peak memory 199480 kb
Host smart-88be4b7c-5b74-4d68-ab4e-356a0828b1ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224036209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2224036209
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1648922472
Short name T335
Test name
Test status
Simulation time 19216780325 ps
CPU time 421.95 seconds
Started Feb 28 04:43:40 PM PST 24
Finished Feb 28 04:50:42 PM PST 24
Peak memory 199424 kb
Host smart-838c55f9-ab20-45cf-9ca4-471078354917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648922472 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1648922472
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.701004899
Short name T552
Test name
Test status
Simulation time 3829894790 ps
CPU time 73.67 seconds
Started Feb 28 04:43:45 PM PST 24
Finished Feb 28 04:44:58 PM PST 24
Peak memory 199620 kb
Host smart-f5bde1e9-466f-4291-878e-ae03dafbdba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701004899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.701004899
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.3135571986
Short name T63
Test name
Test status
Simulation time 85055797530 ps
CPU time 787.18 seconds
Started Feb 28 04:45:54 PM PST 24
Finished Feb 28 04:59:01 PM PST 24
Peak memory 208852 kb
Host smart-a0a3a61c-021b-4a6f-8634-11fd3d03a1d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135571986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.3135571986
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2475615323
Short name T438
Test name
Test status
Simulation time 35412523 ps
CPU time 0.56 seconds
Started Feb 28 04:43:43 PM PST 24
Finished Feb 28 04:43:44 PM PST 24
Peak memory 193780 kb
Host smart-7011b318-805b-4868-b6f4-6e0b655bdd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475615323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2475615323
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.64851406
Short name T169
Test name
Test status
Simulation time 579320589 ps
CPU time 9.74 seconds
Started Feb 28 04:43:43 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 199440 kb
Host smart-81576bf2-a175-4d2f-acd9-5c2e88ad01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64851406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.64851406
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.483638154
Short name T219
Test name
Test status
Simulation time 766618307 ps
CPU time 42.05 seconds
Started Feb 28 04:43:45 PM PST 24
Finished Feb 28 04:44:27 PM PST 24
Peak memory 199488 kb
Host smart-1cdaae8a-d5db-4936-a560-adddf0accb1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483638154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.483638154
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2515601411
Short name T576
Test name
Test status
Simulation time 1616911787 ps
CPU time 60.03 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:44:46 PM PST 24
Peak memory 199368 kb
Host smart-1be64e95-9a0b-43f7-9053-b39580978828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515601411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2515601411
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3167189149
Short name T144
Test name
Test status
Simulation time 4127164837 ps
CPU time 19.7 seconds
Started Feb 28 04:43:40 PM PST 24
Finished Feb 28 04:44:00 PM PST 24
Peak memory 199460 kb
Host smart-62b736d8-8a52-4f23-a620-58f05a90e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167189149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3167189149
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2530681197
Short name T331
Test name
Test status
Simulation time 461921785 ps
CPU time 2.74 seconds
Started Feb 28 04:43:39 PM PST 24
Finished Feb 28 04:43:42 PM PST 24
Peak memory 199420 kb
Host smart-202974bf-8a0f-4fe2-8a61-a17c85dd086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530681197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2530681197
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.864554758
Short name T122
Test name
Test status
Simulation time 57892091945 ps
CPU time 1375.25 seconds
Started Feb 28 04:43:45 PM PST 24
Finished Feb 28 05:06:41 PM PST 24
Peak memory 228256 kb
Host smart-75480b13-adff-4d0d-9b8c-97a13f4d7a0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864554758 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.864554758
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.506208126
Short name T372
Test name
Test status
Simulation time 59584143 ps
CPU time 1.01 seconds
Started Feb 28 04:43:43 PM PST 24
Finished Feb 28 04:43:44 PM PST 24
Peak memory 197868 kb
Host smart-5f2c48d9-3194-4644-9f4a-ac38442d6a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506208126 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.506208126
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1894392255
Short name T463
Test name
Test status
Simulation time 29174417196 ps
CPU time 487.46 seconds
Started Feb 28 04:43:44 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 199456 kb
Host smart-efbda9c8-c248-409e-aac9-354074187f73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894392255 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.1894392255
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4292781154
Short name T263
Test name
Test status
Simulation time 3535161383 ps
CPU time 16.79 seconds
Started Feb 28 04:43:43 PM PST 24
Finished Feb 28 04:44:00 PM PST 24
Peak memory 199528 kb
Host smart-8a232894-3468-4299-8fb8-1098aa036b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292781154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4292781154
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.349636617
Short name T502
Test name
Test status
Simulation time 7332473379 ps
CPU time 165.12 seconds
Started Feb 28 04:45:58 PM PST 24
Finished Feb 28 04:48:43 PM PST 24
Peak memory 229372 kb
Host smart-66c3afe1-47fd-4588-a929-b1d3f26e302d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349636617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.349636617
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3813413565
Short name T141
Test name
Test status
Simulation time 14331406 ps
CPU time 0.56 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:42:54 PM PST 24
Peak memory 193548 kb
Host smart-e4353e38-3344-4fb2-8e0e-71cb60896ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813413565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3813413565
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.221870244
Short name T536
Test name
Test status
Simulation time 4917510140 ps
CPU time 36.86 seconds
Started Feb 28 04:42:56 PM PST 24
Finished Feb 28 04:43:33 PM PST 24
Peak memory 209688 kb
Host smart-45dd477c-01f6-4c9d-bdc1-edb437fc12e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221870244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.221870244
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2065404583
Short name T310
Test name
Test status
Simulation time 1349379929 ps
CPU time 13.68 seconds
Started Feb 28 04:42:46 PM PST 24
Finished Feb 28 04:43:00 PM PST 24
Peak memory 199404 kb
Host smart-ecaa8ccf-1ab0-4d29-8de4-dce37c5870ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065404583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2065404583
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2220294375
Short name T243
Test name
Test status
Simulation time 3225371662 ps
CPU time 170.63 seconds
Started Feb 28 04:42:48 PM PST 24
Finished Feb 28 04:45:39 PM PST 24
Peak memory 199568 kb
Host smart-6d379d16-fabe-410b-8960-27896373ade6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220294375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2220294375
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1744016391
Short name T117
Test name
Test status
Simulation time 2339062760 ps
CPU time 59.22 seconds
Started Feb 28 04:42:47 PM PST 24
Finished Feb 28 04:43:46 PM PST 24
Peak memory 199512 kb
Host smart-66911995-3baf-4b9b-97b6-70098f42bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744016391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1744016391
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1791960339
Short name T368
Test name
Test status
Simulation time 598522474 ps
CPU time 5.8 seconds
Started Feb 28 04:42:55 PM PST 24
Finished Feb 28 04:43:01 PM PST 24
Peak memory 199268 kb
Host smart-ce91f1fe-3b07-4e54-b623-1ef6ab41099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791960339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1791960339
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4063522543
Short name T24
Test name
Test status
Simulation time 83060636 ps
CPU time 0.93 seconds
Started Feb 28 04:42:43 PM PST 24
Finished Feb 28 04:42:45 PM PST 24
Peak memory 217832 kb
Host smart-344f9929-ceb2-4614-a817-97bab52114d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063522543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4063522543
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1425422438
Short name T68
Test name
Test status
Simulation time 1536980657 ps
CPU time 2.32 seconds
Started Feb 28 04:42:46 PM PST 24
Finished Feb 28 04:42:49 PM PST 24
Peak memory 199548 kb
Host smart-11737667-8d06-4d99-bcd2-81cee52fbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425422438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1425422438
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2572862378
Short name T558
Test name
Test status
Simulation time 255037965242 ps
CPU time 1086.96 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 05:00:52 PM PST 24
Peak memory 224868 kb
Host smart-cf2f7f0d-1c47-45d0-b97e-21b4a6126dc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572862378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2572862378
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3755657070
Short name T454
Test name
Test status
Simulation time 159448615 ps
CPU time 0.91 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 04:42:47 PM PST 24
Peak memory 196624 kb
Host smart-098decdb-d81b-4b49-9607-d671fa628e29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755657070 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3755657070
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2553666898
Short name T569
Test name
Test status
Simulation time 8812581196 ps
CPU time 425.5 seconds
Started Feb 28 04:42:44 PM PST 24
Finished Feb 28 04:49:50 PM PST 24
Peak memory 199380 kb
Host smart-06eca562-0b36-4918-8c8d-ceeee3b9bc3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553666898 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.2553666898
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.150866296
Short name T49
Test name
Test status
Simulation time 1246614076 ps
CPU time 58.81 seconds
Started Feb 28 04:42:45 PM PST 24
Finished Feb 28 04:43:45 PM PST 24
Peak memory 199480 kb
Host smart-e8583816-c889-47c4-ae95-bdce4ece2023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150866296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.150866296
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4250470056
Short name T538
Test name
Test status
Simulation time 35513733 ps
CPU time 0.56 seconds
Started Feb 28 04:43:48 PM PST 24
Finished Feb 28 04:43:49 PM PST 24
Peak memory 193856 kb
Host smart-b635a891-cfc5-4352-b951-f74debc0ffc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250470056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4250470056
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2016141456
Short name T396
Test name
Test status
Simulation time 2082626065 ps
CPU time 32.11 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:44:18 PM PST 24
Peak memory 228072 kb
Host smart-9ca9ad53-e74f-4549-8168-34cbffedf5c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016141456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2016141456
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.158255488
Short name T329
Test name
Test status
Simulation time 504492069 ps
CPU time 24.27 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199464 kb
Host smart-b5925ef3-85a1-4cff-bd9a-b6752edacc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158255488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.158255488
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2168961987
Short name T492
Test name
Test status
Simulation time 1803624772 ps
CPU time 46.95 seconds
Started Feb 28 04:43:45 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 199392 kb
Host smart-7119d506-a087-4768-8c8f-d25b73c99021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168961987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2168961987
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.472132032
Short name T580
Test name
Test status
Simulation time 7823094169 ps
CPU time 44.27 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:44:37 PM PST 24
Peak memory 199440 kb
Host smart-36cbd6b5-1526-49b2-b85e-52e249fe344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472132032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.472132032
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.297784628
Short name T388
Test name
Test status
Simulation time 11577030901 ps
CPU time 76.35 seconds
Started Feb 28 04:43:49 PM PST 24
Finished Feb 28 04:45:06 PM PST 24
Peak memory 199520 kb
Host smart-fe1f3a80-a3bd-4b51-87b2-ba0a48a98bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297784628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.297784628
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2513279011
Short name T385
Test name
Test status
Simulation time 1362598177 ps
CPU time 3.95 seconds
Started Feb 28 04:43:44 PM PST 24
Finished Feb 28 04:43:48 PM PST 24
Peak memory 199460 kb
Host smart-12857d0a-4fc6-49ed-bcfe-2d6740732aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513279011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2513279011
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2656510645
Short name T590
Test name
Test status
Simulation time 12400474647 ps
CPU time 328.74 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:49:15 PM PST 24
Peak memory 215528 kb
Host smart-675492a0-3677-4b3f-b842-c6d93cb48a0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656510645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2656510645
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.100116146
Short name T496
Test name
Test status
Simulation time 29859649 ps
CPU time 0.91 seconds
Started Feb 28 04:43:47 PM PST 24
Finished Feb 28 04:43:48 PM PST 24
Peak memory 197368 kb
Host smart-b18c8ef1-dcd3-4a63-96c1-f8d63b7dd458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100116146 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.100116146
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.4153381299
Short name T430
Test name
Test status
Simulation time 8572642933 ps
CPU time 442.66 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:51:09 PM PST 24
Peak memory 199232 kb
Host smart-669c84e3-4b3c-40f3-8da0-d5c3ee95ee23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153381299 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.4153381299
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3474536358
Short name T523
Test name
Test status
Simulation time 782298532 ps
CPU time 37.31 seconds
Started Feb 28 04:43:48 PM PST 24
Finished Feb 28 04:44:26 PM PST 24
Peak memory 199484 kb
Host smart-7541e3ba-6bf7-436f-805e-736bb4768b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474536358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3474536358
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2126772439
Short name T12
Test name
Test status
Simulation time 41529801 ps
CPU time 0.57 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:43:57 PM PST 24
Peak memory 193800 kb
Host smart-6eb0a06a-8338-48aa-b471-86b3f001a35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126772439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2126772439
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3055650007
Short name T304
Test name
Test status
Simulation time 2708353584 ps
CPU time 41.51 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 217520 kb
Host smart-3ab5daff-ed86-4797-9159-333d3fda1d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055650007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3055650007
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3504441482
Short name T365
Test name
Test status
Simulation time 413580988 ps
CPU time 3.58 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:43:50 PM PST 24
Peak memory 199444 kb
Host smart-cc0be3a7-a8f8-493b-89a0-897b8a5fef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504441482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3504441482
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2110623866
Short name T208
Test name
Test status
Simulation time 929694733 ps
CPU time 51.17 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:44 PM PST 24
Peak memory 199332 kb
Host smart-15dc2121-57e2-4abf-b9a8-54166cb3d001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110623866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2110623866
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1836745151
Short name T4
Test name
Test status
Simulation time 62026513522 ps
CPU time 195.95 seconds
Started Feb 28 04:43:46 PM PST 24
Finished Feb 28 04:47:03 PM PST 24
Peak memory 199448 kb
Host smart-a40e8834-81a5-4b83-9b29-860528c3c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836745151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1836745151
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2419332825
Short name T265
Test name
Test status
Simulation time 62408840831 ps
CPU time 90.51 seconds
Started Feb 28 04:43:48 PM PST 24
Finished Feb 28 04:45:18 PM PST 24
Peak memory 199532 kb
Host smart-3e3efbfe-7afd-4dde-b29e-3ddacbe6df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419332825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2419332825
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3920350919
Short name T503
Test name
Test status
Simulation time 893468885 ps
CPU time 3.19 seconds
Started Feb 28 04:43:50 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 199456 kb
Host smart-3e35d30d-5da2-40de-8506-768bff88affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920350919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3920350919
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4184509708
Short name T75
Test name
Test status
Simulation time 44435387943 ps
CPU time 523.31 seconds
Started Feb 28 04:43:50 PM PST 24
Finished Feb 28 04:52:33 PM PST 24
Peak memory 209732 kb
Host smart-19d1a9ac-b6a4-43a6-aec2-017f83d16388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184509708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4184509708
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3780682244
Short name T30
Test name
Test status
Simulation time 52639981 ps
CPU time 1 seconds
Started Feb 28 04:43:49 PM PST 24
Finished Feb 28 04:43:51 PM PST 24
Peak memory 197296 kb
Host smart-4adbe099-861d-4f49-a898-9f638274f9d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780682244 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3780682244
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3069465348
Short name T599
Test name
Test status
Simulation time 42845189377 ps
CPU time 479.19 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 199380 kb
Host smart-3f971f18-7105-4157-9cf0-55e1abecbb51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069465348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3069465348
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3066979806
Short name T162
Test name
Test status
Simulation time 13279902660 ps
CPU time 40.96 seconds
Started Feb 28 04:43:48 PM PST 24
Finished Feb 28 04:44:30 PM PST 24
Peak memory 199464 kb
Host smart-1c35cfbd-af0e-4922-a7fb-b8901561e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066979806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3066979806
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1769059355
Short name T415
Test name
Test status
Simulation time 44015492 ps
CPU time 0.57 seconds
Started Feb 28 04:43:50 PM PST 24
Finished Feb 28 04:43:50 PM PST 24
Peak memory 194012 kb
Host smart-cdaa5de7-2277-4fae-be20-b354abb1a4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769059355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1769059355
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2453598116
Short name T315
Test name
Test status
Simulation time 1378754310 ps
CPU time 31.01 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:44:23 PM PST 24
Peak memory 231804 kb
Host smart-e8a1429c-8b57-4fd8-84eb-bdacdb29b636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453598116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2453598116
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1982396070
Short name T181
Test name
Test status
Simulation time 1210409229 ps
CPU time 13.48 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199428 kb
Host smart-107b40e6-0fcf-4a55-ae24-69e724dfce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982396070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1982396070
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1842321171
Short name T48
Test name
Test status
Simulation time 1495461456 ps
CPU time 40.17 seconds
Started Feb 28 04:43:49 PM PST 24
Finished Feb 28 04:44:29 PM PST 24
Peak memory 199396 kb
Host smart-5c36e624-4f51-40b9-8c26-eaa1cbbb3455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842321171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1842321171
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1231541930
Short name T314
Test name
Test status
Simulation time 6401213182 ps
CPU time 57.05 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:44:48 PM PST 24
Peak memory 199508 kb
Host smart-a5c48aa6-63a1-469b-9128-87779672b3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231541930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1231541930
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1590732617
Short name T218
Test name
Test status
Simulation time 1202080508 ps
CPU time 56.56 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:44:48 PM PST 24
Peak memory 199392 kb
Host smart-bc55c348-34cf-4f85-9ee0-d885adb887dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590732617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1590732617
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1547467532
Short name T283
Test name
Test status
Simulation time 1352583173 ps
CPU time 3.28 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:43:54 PM PST 24
Peak memory 199484 kb
Host smart-42cf07da-74f2-4729-91f8-389ef5597fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547467532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1547467532
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1538364920
Short name T449
Test name
Test status
Simulation time 12934131279 ps
CPU time 144.13 seconds
Started Feb 28 04:43:50 PM PST 24
Finished Feb 28 04:46:14 PM PST 24
Peak memory 199556 kb
Host smart-9410d8d6-b6b2-4998-9e3a-8c4d88e09756
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538364920 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1538364920
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1772659558
Short name T172
Test name
Test status
Simulation time 64153759 ps
CPU time 1.26 seconds
Started Feb 28 04:43:54 PM PST 24
Finished Feb 28 04:43:55 PM PST 24
Peak memory 198304 kb
Host smart-281f0700-2c03-4332-b4bb-9d96b65bd771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772659558 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1772659558
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2183416331
Short name T386
Test name
Test status
Simulation time 152666864087 ps
CPU time 463.6 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:51:40 PM PST 24
Peak memory 199452 kb
Host smart-f0c5455c-22d0-421f-856c-557014c66f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183416331 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.2183416331
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2990701361
Short name T437
Test name
Test status
Simulation time 5002720985 ps
CPU time 32.03 seconds
Started Feb 28 04:43:49 PM PST 24
Finished Feb 28 04:44:22 PM PST 24
Peak memory 199496 kb
Host smart-658ab314-911a-43c2-88c1-e0ddee6c28d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990701361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2990701361
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.592063676
Short name T262
Test name
Test status
Simulation time 13723235 ps
CPU time 0.59 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 194060 kb
Host smart-c575baad-a2fa-4563-97a3-e4187f7d56ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592063676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.592063676
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4038944603
Short name T278
Test name
Test status
Simulation time 962722900 ps
CPU time 25.24 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:44:22 PM PST 24
Peak memory 199452 kb
Host smart-9373b192-5ce6-4f6a-809b-234c4dab1e07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038944603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4038944603
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.874765418
Short name T271
Test name
Test status
Simulation time 4319436603 ps
CPU time 38.94 seconds
Started Feb 28 04:43:55 PM PST 24
Finished Feb 28 04:44:34 PM PST 24
Peak memory 199608 kb
Host smart-1ef423de-8987-4a0b-aabe-a3639d159527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874765418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.874765418
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2906910079
Short name T316
Test name
Test status
Simulation time 155673142 ps
CPU time 8.33 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:01 PM PST 24
Peak memory 199432 kb
Host smart-7a1e6334-17a2-4103-88da-40827d909cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906910079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2906910079
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3873635601
Short name T293
Test name
Test status
Simulation time 13019140679 ps
CPU time 138.15 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:46:14 PM PST 24
Peak memory 199540 kb
Host smart-feb485f3-d3d7-45b8-984b-0363555e8617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873635601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3873635601
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3873813958
Short name T504
Test name
Test status
Simulation time 1573329935 ps
CPU time 84.36 seconds
Started Feb 28 04:43:59 PM PST 24
Finished Feb 28 04:45:24 PM PST 24
Peak memory 199448 kb
Host smart-a6ad9e70-40bd-4c28-9d2e-fa9837cdc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873813958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3873813958
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3546700460
Short name T379
Test name
Test status
Simulation time 170435298 ps
CPU time 3.73 seconds
Started Feb 28 04:43:49 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 199364 kb
Host smart-f2ad4160-9e8a-45ad-bcfa-56a3108541bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546700460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3546700460
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3874902270
Short name T72
Test name
Test status
Simulation time 51139862445 ps
CPU time 678.41 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:55:11 PM PST 24
Peak memory 231508 kb
Host smart-3b4440bb-c9e5-44a3-98d4-87f88ab0d0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874902270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3874902270
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.586889882
Short name T77
Test name
Test status
Simulation time 141664769 ps
CPU time 1.27 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:43:53 PM PST 24
Peak memory 198472 kb
Host smart-19f5bc7d-675f-40f6-8f25-5357d7c7b0a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586889882 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.586889882
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1026799581
Short name T239
Test name
Test status
Simulation time 42716791821 ps
CPU time 498.63 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:52:11 PM PST 24
Peak memory 199460 kb
Host smart-72fbecce-7ac9-4f35-897f-4f05703e7c88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026799581 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.1026799581
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1473914923
Short name T1
Test name
Test status
Simulation time 2053261393 ps
CPU time 9.22 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:02 PM PST 24
Peak memory 199392 kb
Host smart-57976a30-3c71-49fa-8902-47946617df44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473914923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1473914923
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1031388778
Short name T455
Test name
Test status
Simulation time 12139444 ps
CPU time 0.58 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 194036 kb
Host smart-772aa9bc-c422-402a-a8fc-262d96066de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031388778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1031388778
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.804700114
Short name T184
Test name
Test status
Simulation time 213045036 ps
CPU time 6.83 seconds
Started Feb 28 04:44:00 PM PST 24
Finished Feb 28 04:44:07 PM PST 24
Peak memory 199416 kb
Host smart-7148cfa7-931b-41f6-95e9-e3492ff18dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804700114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.804700114
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4039835139
Short name T37
Test name
Test status
Simulation time 132023125 ps
CPU time 1.62 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:43:55 PM PST 24
Peak memory 199400 kb
Host smart-4e690157-676c-4355-8fed-6680a141d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039835139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4039835139
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1247672026
Short name T543
Test name
Test status
Simulation time 144944717 ps
CPU time 7.71 seconds
Started Feb 28 04:43:54 PM PST 24
Finished Feb 28 04:44:01 PM PST 24
Peak memory 199420 kb
Host smart-2c12689b-ef67-4c7e-ad1a-8deffa7aa494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247672026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1247672026
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2017045027
Short name T443
Test name
Test status
Simulation time 24748015348 ps
CPU time 105.9 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:45:38 PM PST 24
Peak memory 199472 kb
Host smart-725a2da0-936b-480b-a180-42bf31d16af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017045027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2017045027
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2640073116
Short name T145
Test name
Test status
Simulation time 8247462157 ps
CPU time 86.46 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:45:18 PM PST 24
Peak memory 199556 kb
Host smart-e2941273-6e58-4d04-806e-fd1d65f48849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640073116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2640073116
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.411686219
Short name T153
Test name
Test status
Simulation time 258112204 ps
CPU time 1.82 seconds
Started Feb 28 04:43:55 PM PST 24
Finished Feb 28 04:43:57 PM PST 24
Peak memory 199300 kb
Host smart-3bd3d599-85d7-48ef-ad0b-1910e8a36685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411686219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.411686219
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1458151773
Short name T291
Test name
Test status
Simulation time 39394199825 ps
CPU time 179.26 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:46:55 PM PST 24
Peak memory 217472 kb
Host smart-fe5bc7e3-60de-4b64-a3a4-bd427e608ab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458151773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1458151773
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1384827292
Short name T592
Test name
Test status
Simulation time 31377745 ps
CPU time 0.98 seconds
Started Feb 28 04:43:54 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 196656 kb
Host smart-57b9df6a-b965-4bf1-9638-f7d66f775c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384827292 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1384827292
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3650393649
Short name T451
Test name
Test status
Simulation time 2177938612 ps
CPU time 26.01 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:44:23 PM PST 24
Peak memory 199536 kb
Host smart-fb81aa37-ca92-4e2b-8a24-3a8957b4f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650393649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3650393649
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2076521669
Short name T572
Test name
Test status
Simulation time 10698958 ps
CPU time 0.55 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 194044 kb
Host smart-0945d0b5-be1b-4934-9c8d-a45a0273b861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076521669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2076521669
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1415556109
Short name T541
Test name
Test status
Simulation time 995682791 ps
CPU time 8.84 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:44:07 PM PST 24
Peak memory 199436 kb
Host smart-4a2292b2-be3a-42d2-9f83-d2242fcb0ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415556109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1415556109
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1655030184
Short name T97
Test name
Test status
Simulation time 1211519866 ps
CPU time 55.07 seconds
Started Feb 28 04:43:52 PM PST 24
Finished Feb 28 04:44:47 PM PST 24
Peak memory 199444 kb
Host smart-68356810-d110-4a76-896d-b031d8381f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655030184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1655030184
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.983474475
Short name T306
Test name
Test status
Simulation time 18574428709 ps
CPU time 74.59 seconds
Started Feb 28 04:43:51 PM PST 24
Finished Feb 28 04:45:06 PM PST 24
Peak memory 199524 kb
Host smart-af653889-9ce4-4325-b975-3803c1f12a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983474475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.983474475
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2356757004
Short name T408
Test name
Test status
Simulation time 795225647 ps
CPU time 38.68 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 199368 kb
Host smart-076badf4-15e8-4228-89af-c7307f371a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356757004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2356757004
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.517651441
Short name T199
Test name
Test status
Simulation time 8574936448 ps
CPU time 56.7 seconds
Started Feb 28 04:43:53 PM PST 24
Finished Feb 28 04:44:50 PM PST 24
Peak memory 199560 kb
Host smart-cbd62ac3-57ce-4e5b-9a1f-4a91cccbdddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517651441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.517651441
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2087408663
Short name T67
Test name
Test status
Simulation time 770756108 ps
CPU time 2.19 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:44:00 PM PST 24
Peak memory 199408 kb
Host smart-3a42c0ad-3702-47ec-b84c-970f41bff56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087408663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2087408663
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3440308561
Short name T467
Test name
Test status
Simulation time 52768539442 ps
CPU time 153.57 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:46:31 PM PST 24
Peak memory 207640 kb
Host smart-ef7d655a-3b00-44aa-8b05-d2504592f6aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440308561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3440308561
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4087870497
Short name T246
Test name
Test status
Simulation time 27994158 ps
CPU time 0.98 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:43:59 PM PST 24
Peak memory 198056 kb
Host smart-45d48b81-d957-4481-8408-2cc20a4e11d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087870497 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4087870497
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.792491452
Short name T404
Test name
Test status
Simulation time 8624570465 ps
CPU time 440.68 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:51:18 PM PST 24
Peak memory 199380 kb
Host smart-faed2b76-51a2-4041-8df3-c29209148138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792491452 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_sha_vectors.792491452
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1937553816
Short name T257
Test name
Test status
Simulation time 7304461845 ps
CPU time 61.16 seconds
Started Feb 28 04:44:00 PM PST 24
Finished Feb 28 04:45:01 PM PST 24
Peak memory 199612 kb
Host smart-55fe62f8-193e-4935-9af9-35c9997e39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937553816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1937553816
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2930365598
Short name T190
Test name
Test status
Simulation time 52788709 ps
CPU time 0.63 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:43:59 PM PST 24
Peak memory 194836 kb
Host smart-58e455a5-c201-45db-9957-e1c79a276693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930365598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2930365598
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1120763096
Short name T367
Test name
Test status
Simulation time 1048456728 ps
CPU time 7.4 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 215792 kb
Host smart-6f37c235-2c96-4e1f-aefa-1468d173aed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120763096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1120763096
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3557529199
Short name T116
Test name
Test status
Simulation time 17675965541 ps
CPU time 42.97 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199468 kb
Host smart-7f34785b-c21d-46da-90f5-bd24b50f9641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557529199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3557529199
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2596193543
Short name T359
Test name
Test status
Simulation time 743670045 ps
CPU time 39.49 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:44:38 PM PST 24
Peak memory 199428 kb
Host smart-80aa667b-83b5-4bce-8048-23f31c67b51a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596193543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2596193543
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1413531039
Short name T235
Test name
Test status
Simulation time 7894852134 ps
CPU time 103.64 seconds
Started Feb 28 04:44:06 PM PST 24
Finished Feb 28 04:45:50 PM PST 24
Peak memory 199484 kb
Host smart-892949f7-0fa9-455b-b2d8-ab03922894a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413531039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1413531039
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1234283854
Short name T261
Test name
Test status
Simulation time 1315722847 ps
CPU time 71.2 seconds
Started Feb 28 04:43:58 PM PST 24
Finished Feb 28 04:45:09 PM PST 24
Peak memory 199404 kb
Host smart-a70cdf10-91c5-41ce-8c75-898c3dc4da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234283854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1234283854
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4060866505
Short name T164
Test name
Test status
Simulation time 37627189 ps
CPU time 1.11 seconds
Started Feb 28 04:43:55 PM PST 24
Finished Feb 28 04:43:56 PM PST 24
Peak memory 199060 kb
Host smart-7496205d-c268-4067-91cf-fb5ddc90c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060866505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4060866505
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3185090757
Short name T143
Test name
Test status
Simulation time 1496615899 ps
CPU time 43.45 seconds
Started Feb 28 04:43:56 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199508 kb
Host smart-a00651bc-a354-46cb-9c7e-646f4726377c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185090757 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3185090757
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.322809013
Short name T196
Test name
Test status
Simulation time 114734429 ps
CPU time 1.19 seconds
Started Feb 28 04:43:59 PM PST 24
Finished Feb 28 04:44:01 PM PST 24
Peak memory 198184 kb
Host smart-8b1cd7a7-e7f9-4e44-8a1f-f8496dc676a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322809013 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.322809013
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2730287803
Short name T213
Test name
Test status
Simulation time 9221854513 ps
CPU time 457.01 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 199428 kb
Host smart-f34b470b-6a4a-42f7-a53d-f8c83805d897
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730287803 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2730287803
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.858496399
Short name T418
Test name
Test status
Simulation time 7245561828 ps
CPU time 19.9 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:44:17 PM PST 24
Peak memory 199548 kb
Host smart-cff91c64-70dd-472b-a643-824aec5772ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858496399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.858496399
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2060600366
Short name T317
Test name
Test status
Simulation time 42721294 ps
CPU time 0.61 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:03 PM PST 24
Peak memory 194852 kb
Host smart-101e466d-acc9-49cb-9523-829a459e756b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060600366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2060600366
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2330652053
Short name T29
Test name
Test status
Simulation time 771752094 ps
CPU time 22.58 seconds
Started Feb 28 04:43:55 PM PST 24
Finished Feb 28 04:44:17 PM PST 24
Peak memory 199408 kb
Host smart-fed51853-e9ab-4c9a-9c3a-ede6d566f6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330652053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2330652053
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3868039656
Short name T344
Test name
Test status
Simulation time 8109976431 ps
CPU time 38.54 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199460 kb
Host smart-121066db-445a-4ffa-959a-89b3e659744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868039656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3868039656
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.961623921
Short name T130
Test name
Test status
Simulation time 2824529251 ps
CPU time 38.7 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199480 kb
Host smart-35f7c84a-c1a9-4564-b20a-b6feb7c992cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961623921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.961623921
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2571140979
Short name T311
Test name
Test status
Simulation time 499113272 ps
CPU time 6.23 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:07 PM PST 24
Peak memory 199324 kb
Host smart-f99104a0-4367-4a8a-95e1-77ffb8fbce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571140979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2571140979
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3436168197
Short name T34
Test name
Test status
Simulation time 1023428030 ps
CPU time 15.88 seconds
Started Feb 28 04:43:57 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 199496 kb
Host smart-21deb698-a3af-4f24-b5cf-86f197d76b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436168197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3436168197
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2891312383
Short name T216
Test name
Test status
Simulation time 6507806257 ps
CPU time 4.48 seconds
Started Feb 28 04:43:55 PM PST 24
Finished Feb 28 04:44:00 PM PST 24
Peak memory 199476 kb
Host smart-77e49ec8-e099-472f-9a9b-d99784f0c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891312383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2891312383
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.373567589
Short name T40
Test name
Test status
Simulation time 56423947379 ps
CPU time 1363.16 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 05:06:44 PM PST 24
Peak memory 241128 kb
Host smart-912bf3ef-bc92-4d85-a02a-0c0ce869478b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373567589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.373567589
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2439109496
Short name T296
Test name
Test status
Simulation time 165001407 ps
CPU time 0.92 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:02 PM PST 24
Peak memory 197440 kb
Host smart-48eca07c-f80e-4025-a512-74ac21152eb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439109496 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2439109496
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1054419504
Short name T377
Test name
Test status
Simulation time 106743050752 ps
CPU time 457.79 seconds
Started Feb 28 04:43:59 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 199452 kb
Host smart-9f6ba73c-8062-47f8-81c5-462b9e37e3af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054419504 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1054419504
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.481586638
Short name T250
Test name
Test status
Simulation time 654588591 ps
CPU time 25.59 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:28 PM PST 24
Peak memory 199540 kb
Host smart-12a111e7-3fc9-4c7d-aa9b-cb2893c7d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481586638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.481586638
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3947867350
Short name T185
Test name
Test status
Simulation time 18792359 ps
CPU time 0.57 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:44:03 PM PST 24
Peak memory 193832 kb
Host smart-ee461ffb-a222-4008-b58e-3b81212e34a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947867350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3947867350
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1688599732
Short name T10
Test name
Test status
Simulation time 1417706504 ps
CPU time 10.84 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 211252 kb
Host smart-6a64562f-e487-4560-9b74-49353b23b2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688599732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1688599732
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1622471810
Short name T155
Test name
Test status
Simulation time 5975787912 ps
CPU time 42.25 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:43 PM PST 24
Peak memory 199464 kb
Host smart-d6cbf1eb-fc1e-4cf0-a1ed-7f559c3f8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622471810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1622471810
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.968381671
Short name T248
Test name
Test status
Simulation time 1206870242 ps
CPU time 15.19 seconds
Started Feb 28 04:44:00 PM PST 24
Finished Feb 28 04:44:15 PM PST 24
Peak memory 199532 kb
Host smart-f38bdba2-c508-4587-8172-77886b1ad808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968381671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.968381671
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3812064928
Short name T300
Test name
Test status
Simulation time 1194153425 ps
CPU time 58.17 seconds
Started Feb 28 04:44:00 PM PST 24
Finished Feb 28 04:44:59 PM PST 24
Peak memory 199440 kb
Host smart-dcb25c27-e4d2-4c56-b629-b04f2ea709df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812064928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3812064928
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.611401095
Short name T211
Test name
Test status
Simulation time 64188071 ps
CPU time 0.67 seconds
Started Feb 28 04:44:00 PM PST 24
Finished Feb 28 04:44:01 PM PST 24
Peak memory 195180 kb
Host smart-eca8f645-6eba-425d-8a70-8b78d7d7211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611401095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.611401095
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1895732607
Short name T166
Test name
Test status
Simulation time 557406022 ps
CPU time 3.48 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:06 PM PST 24
Peak memory 199408 kb
Host smart-64714f77-dbaf-4f84-9438-656195e052d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895732607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1895732607
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.535239777
Short name T473
Test name
Test status
Simulation time 115960109484 ps
CPU time 1354.1 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 05:06:37 PM PST 24
Peak memory 240348 kb
Host smart-62cf8942-69cd-4b25-ae9b-a0138e022a72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535239777 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.535239777
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.563296834
Short name T233
Test name
Test status
Simulation time 228678461 ps
CPU time 1.22 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:03 PM PST 24
Peak memory 198680 kb
Host smart-f337d07d-a745-414e-9bd6-3af26997a993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563296834 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.563296834
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1086704340
Short name T351
Test name
Test status
Simulation time 28717515256 ps
CPU time 446.25 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 199436 kb
Host smart-441d5da9-6f03-4247-8037-242ea0edc62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086704340 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1086704340
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2908075074
Short name T186
Test name
Test status
Simulation time 9979112439 ps
CPU time 79.27 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:45:23 PM PST 24
Peak memory 199340 kb
Host smart-f1ecc591-ac1a-4f60-94a5-954cf016f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908075074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2908075074
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2104900995
Short name T231
Test name
Test status
Simulation time 42174825 ps
CPU time 0.55 seconds
Started Feb 28 04:44:04 PM PST 24
Finished Feb 28 04:44:05 PM PST 24
Peak memory 193672 kb
Host smart-be8c2026-f8be-4df3-bd37-46ad16cad5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104900995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2104900995
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3195295998
Short name T380
Test name
Test status
Simulation time 6244863458 ps
CPU time 49.45 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:44:53 PM PST 24
Peak memory 232316 kb
Host smart-669c7583-b857-4d80-b915-9096a777d3a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195295998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3195295998
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1772234018
Short name T375
Test name
Test status
Simulation time 2139570498 ps
CPU time 39.39 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:42 PM PST 24
Peak memory 199432 kb
Host smart-ceec4880-9e95-45b9-b320-401ba4a17f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772234018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1772234018
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2056364096
Short name T416
Test name
Test status
Simulation time 2811712921 ps
CPU time 37.72 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 199392 kb
Host smart-a9317730-88af-4bb0-a4cd-cfffd86f54b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056364096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2056364096
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4049099012
Short name T490
Test name
Test status
Simulation time 2310971842 ps
CPU time 25.76 seconds
Started Feb 28 04:44:01 PM PST 24
Finished Feb 28 04:44:27 PM PST 24
Peak memory 199428 kb
Host smart-c8324c77-1f4c-4897-beea-f488448bcaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049099012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4049099012
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1880102125
Short name T477
Test name
Test status
Simulation time 3907597614 ps
CPU time 59.76 seconds
Started Feb 28 04:44:04 PM PST 24
Finished Feb 28 04:45:04 PM PST 24
Peak memory 199584 kb
Host smart-6a4a0fe3-0f9a-4f4d-a75a-2406d5148996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880102125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1880102125
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1791730419
Short name T352
Test name
Test status
Simulation time 119051499 ps
CPU time 0.84 seconds
Started Feb 28 04:44:02 PM PST 24
Finished Feb 28 04:44:03 PM PST 24
Peak memory 196672 kb
Host smart-62c8f708-c92d-40c5-b391-d90996672426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791730419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1791730419
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4002857712
Short name T96
Test name
Test status
Simulation time 20487808087 ps
CPU time 259.97 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:48:23 PM PST 24
Peak memory 199392 kb
Host smart-c8233fbc-bf9e-475a-9e91-6f094137c7c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002857712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4002857712
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1506097716
Short name T269
Test name
Test status
Simulation time 157483662 ps
CPU time 0.85 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 196280 kb
Host smart-6838f9d7-6de4-465c-a054-c34a26e8efae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506097716 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1506097716
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2982155076
Short name T210
Test name
Test status
Simulation time 29341098979 ps
CPU time 489.3 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:52:13 PM PST 24
Peak memory 199508 kb
Host smart-bc67935b-5380-4c10-ac67-2e876348e0ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982155076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.2982155076
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2341277509
Short name T289
Test name
Test status
Simulation time 351351654 ps
CPU time 5.01 seconds
Started Feb 28 04:44:04 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199492 kb
Host smart-74f48b45-cd1d-427e-b511-e5660500fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341277509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2341277509
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3184142355
Short name T193
Test name
Test status
Simulation time 104928042 ps
CPU time 0.59 seconds
Started Feb 28 04:42:49 PM PST 24
Finished Feb 28 04:42:50 PM PST 24
Peak memory 193884 kb
Host smart-1eaf5b6e-d06f-4561-bdd1-f9356b8bbbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184142355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3184142355
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.120723920
Short name T489
Test name
Test status
Simulation time 3655170449 ps
CPU time 48.43 seconds
Started Feb 28 04:42:47 PM PST 24
Finished Feb 28 04:43:35 PM PST 24
Peak memory 199424 kb
Host smart-41595e00-6da7-4758-810a-144a709634f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120723920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.120723920
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1098820767
Short name T103
Test name
Test status
Simulation time 851737111 ps
CPU time 44.34 seconds
Started Feb 28 04:42:56 PM PST 24
Finished Feb 28 04:43:40 PM PST 24
Peak memory 199424 kb
Host smart-ca6af09b-6892-4d4e-8b82-90657d5f07d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098820767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1098820767
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.839544488
Short name T204
Test name
Test status
Simulation time 7489921852 ps
CPU time 137 seconds
Started Feb 28 04:42:47 PM PST 24
Finished Feb 28 04:45:04 PM PST 24
Peak memory 199608 kb
Host smart-bde2a930-25bd-4b57-8374-819850990a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839544488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.839544488
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3214251778
Short name T595
Test name
Test status
Simulation time 26360290966 ps
CPU time 84.72 seconds
Started Feb 28 04:42:44 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 199544 kb
Host smart-9f1f0fba-40fd-42c1-83dc-5a6232981e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214251778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3214251778
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.930146741
Short name T26
Test name
Test status
Simulation time 35564292 ps
CPU time 0.79 seconds
Started Feb 28 04:42:54 PM PST 24
Finished Feb 28 04:42:55 PM PST 24
Peak memory 216556 kb
Host smart-5c55e78c-35a2-4edf-86c0-bc80ab0f5880
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930146741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.930146741
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3750136269
Short name T461
Test name
Test status
Simulation time 189874792 ps
CPU time 4.42 seconds
Started Feb 28 04:42:50 PM PST 24
Finished Feb 28 04:42:55 PM PST 24
Peak memory 199408 kb
Host smart-79f3719c-4ef2-430b-93f2-58a99fc23d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750136269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3750136269
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3610128249
Short name T126
Test name
Test status
Simulation time 70972629721 ps
CPU time 1224.4 seconds
Started Feb 28 04:42:48 PM PST 24
Finished Feb 28 05:03:13 PM PST 24
Peak memory 223984 kb
Host smart-03144b2e-c752-4191-9e54-8cd7ce29db01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610128249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3610128249
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3515481967
Short name T587
Test name
Test status
Simulation time 349033017 ps
CPU time 0.96 seconds
Started Feb 28 04:42:47 PM PST 24
Finished Feb 28 04:42:48 PM PST 24
Peak memory 197252 kb
Host smart-65bcfe6f-a93b-4ccf-9ad1-29039f8e892f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515481967 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3515481967
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1448007726
Short name T312
Test name
Test status
Simulation time 123862273464 ps
CPU time 559.17 seconds
Started Feb 28 04:42:50 PM PST 24
Finished Feb 28 04:52:09 PM PST 24
Peak memory 199504 kb
Host smart-35ae5c14-7395-4d03-a47a-b8120aa5cac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448007726 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1448007726
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3851802090
Short name T511
Test name
Test status
Simulation time 24969785 ps
CPU time 0.69 seconds
Started Feb 28 04:42:51 PM PST 24
Finished Feb 28 04:42:51 PM PST 24
Peak memory 195232 kb
Host smart-262c0d4c-cfac-41a3-8d40-d615f63ee6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851802090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3851802090
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3571862339
Short name T525
Test name
Test status
Simulation time 22142082 ps
CPU time 0.61 seconds
Started Feb 28 04:44:10 PM PST 24
Finished Feb 28 04:44:11 PM PST 24
Peak memory 195076 kb
Host smart-778527d1-69e2-4749-b14e-8c1b839b2fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571862339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3571862339
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1126175480
Short name T410
Test name
Test status
Simulation time 26575654299 ps
CPU time 47.84 seconds
Started Feb 28 04:44:05 PM PST 24
Finished Feb 28 04:44:53 PM PST 24
Peak memory 232312 kb
Host smart-59d94859-1195-4144-b4b6-471ee573c394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126175480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1126175480
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1081627323
Short name T391
Test name
Test status
Simulation time 8356118043 ps
CPU time 44.52 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:54 PM PST 24
Peak memory 199520 kb
Host smart-e52200b2-be09-437d-9852-62fcfa8e6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081627323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1081627323
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2073470632
Short name T452
Test name
Test status
Simulation time 10409749202 ps
CPU time 134.79 seconds
Started Feb 28 04:44:03 PM PST 24
Finished Feb 28 04:46:18 PM PST 24
Peak memory 199544 kb
Host smart-f6a968d2-0c3b-4511-b5e9-c77fc0587e84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073470632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2073470632
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1769750081
Short name T334
Test name
Test status
Simulation time 113622916 ps
CPU time 3.27 seconds
Started Feb 28 04:44:06 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199408 kb
Host smart-3afc283b-0e96-4292-bf24-5c06570d05f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769750081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1769750081
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3176119666
Short name T539
Test name
Test status
Simulation time 208238171 ps
CPU time 3.83 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 198820 kb
Host smart-9c71e76c-9725-433e-926b-fa9b4c327067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176119666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3176119666
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2959874548
Short name T95
Test name
Test status
Simulation time 164812013 ps
CPU time 2.04 seconds
Started Feb 28 04:44:04 PM PST 24
Finished Feb 28 04:44:07 PM PST 24
Peak memory 199448 kb
Host smart-86eeb3f0-c75d-4d25-a421-2f2f78351ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959874548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2959874548
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3031650273
Short name T252
Test name
Test status
Simulation time 92056084502 ps
CPU time 2335.96 seconds
Started Feb 28 04:44:07 PM PST 24
Finished Feb 28 05:23:04 PM PST 24
Peak memory 207752 kb
Host smart-3c9e9777-4410-42db-b6af-c4c327144d09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031650273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3031650273
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.324361718
Short name T8
Test name
Test status
Simulation time 26605149 ps
CPU time 0.97 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:11 PM PST 24
Peak memory 196872 kb
Host smart-7d7c6607-7d48-4fc7-9499-57338318285d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324361718 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.324361718
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1403881402
Short name T360
Test name
Test status
Simulation time 26113398830 ps
CPU time 471.89 seconds
Started Feb 28 04:44:06 PM PST 24
Finished Feb 28 04:51:58 PM PST 24
Peak memory 199524 kb
Host smart-54824e75-4c93-400f-bf6b-0efb1b43903b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403881402 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1403881402
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1822711860
Short name T123
Test name
Test status
Simulation time 2690170332 ps
CPU time 86.21 seconds
Started Feb 28 04:44:08 PM PST 24
Finished Feb 28 04:45:35 PM PST 24
Peak memory 199544 kb
Host smart-f29d2fb4-ea98-4269-821d-40f87891246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822711860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1822711860
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1461600782
Short name T524
Test name
Test status
Simulation time 13392865 ps
CPU time 0.58 seconds
Started Feb 28 04:44:12 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 193808 kb
Host smart-a403cf44-c404-4143-9a63-2252cf64d356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461600782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1461600782
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2940651426
Short name T303
Test name
Test status
Simulation time 99845295 ps
CPU time 2.05 seconds
Started Feb 28 04:44:07 PM PST 24
Finished Feb 28 04:44:09 PM PST 24
Peak memory 207532 kb
Host smart-092d5429-895a-4a21-a79b-08d5ab377437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940651426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2940651426
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3682852568
Short name T348
Test name
Test status
Simulation time 1184537075 ps
CPU time 56.27 seconds
Started Feb 28 04:44:05 PM PST 24
Finished Feb 28 04:45:02 PM PST 24
Peak memory 199492 kb
Host smart-14c4d5c1-c0df-4cbb-87af-77e998e86985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682852568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3682852568
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1230856945
Short name T332
Test name
Test status
Simulation time 6008270957 ps
CPU time 81.85 seconds
Started Feb 28 04:44:07 PM PST 24
Finished Feb 28 04:45:29 PM PST 24
Peak memory 199556 kb
Host smart-15203171-4169-4b6f-b764-7d77c3e42f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230856945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1230856945
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2220133792
Short name T497
Test name
Test status
Simulation time 13160459639 ps
CPU time 173.07 seconds
Started Feb 28 04:44:08 PM PST 24
Finished Feb 28 04:47:01 PM PST 24
Peak memory 199480 kb
Host smart-0513356e-8744-4f1f-9c56-47dfb2704b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220133792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2220133792
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3259664444
Short name T383
Test name
Test status
Simulation time 9953472527 ps
CPU time 95.52 seconds
Started Feb 28 04:44:08 PM PST 24
Finished Feb 28 04:45:44 PM PST 24
Peak memory 199496 kb
Host smart-4eac8f3a-811f-44d3-95dd-3fca4a68c319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259664444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3259664444
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.633102989
Short name T594
Test name
Test status
Simulation time 581538905 ps
CPU time 2.27 seconds
Started Feb 28 04:44:08 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199400 kb
Host smart-9584e7c8-780f-41d9-a15e-f873f9c45be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633102989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.633102989
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2486934678
Short name T369
Test name
Test status
Simulation time 112438768569 ps
CPU time 1420.51 seconds
Started Feb 28 04:44:08 PM PST 24
Finished Feb 28 05:07:49 PM PST 24
Peak memory 199572 kb
Host smart-844c4724-2632-4c2c-8a79-ac9d088812c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486934678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2486934678
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1290898860
Short name T555
Test name
Test status
Simulation time 134632716 ps
CPU time 1.16 seconds
Started Feb 28 04:44:10 PM PST 24
Finished Feb 28 04:44:11 PM PST 24
Peak memory 198280 kb
Host smart-95807a2a-864c-4376-befd-582e70aee664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290898860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1290898860
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1920071364
Short name T363
Test name
Test status
Simulation time 40420050733 ps
CPU time 430.34 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:51:19 PM PST 24
Peak memory 199364 kb
Host smart-e4144f79-e0a6-4820-a77f-3a5a5255865a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920071364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1920071364
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3749734083
Short name T353
Test name
Test status
Simulation time 20236498118 ps
CPU time 71.07 seconds
Started Feb 28 04:44:07 PM PST 24
Finished Feb 28 04:45:18 PM PST 24
Peak memory 199440 kb
Host smart-cdb8341e-1453-4df6-959c-45581debca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749734083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3749734083
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3694498999
Short name T191
Test name
Test status
Simulation time 24023821 ps
CPU time 0.57 seconds
Started Feb 28 04:44:15 PM PST 24
Finished Feb 28 04:44:15 PM PST 24
Peak memory 193748 kb
Host smart-eda6b137-4968-4013-962f-efe1a545c67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694498999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3694498999
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3595857101
Short name T364
Test name
Test status
Simulation time 1663655468 ps
CPU time 3.49 seconds
Started Feb 28 04:44:10 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 199512 kb
Host smart-ef873e74-3983-445e-a06e-d57eeeae3a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595857101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3595857101
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1819033791
Short name T392
Test name
Test status
Simulation time 37735800921 ps
CPU time 37.24 seconds
Started Feb 28 04:44:14 PM PST 24
Finished Feb 28 04:44:51 PM PST 24
Peak memory 199520 kb
Host smart-685793c0-94ec-460a-91bb-c2036ce43963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819033791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1819033791
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2398111609
Short name T194
Test name
Test status
Simulation time 872960736 ps
CPU time 22.6 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 199396 kb
Host smart-af85132e-1bbb-4b7e-8168-fceeaad0731f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398111609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2398111609
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2243185451
Short name T602
Test name
Test status
Simulation time 9327767589 ps
CPU time 114.47 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:46:11 PM PST 24
Peak memory 199532 kb
Host smart-0718f28d-a8e6-45af-8c85-7b602e77eb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243185451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2243185451
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3544500028
Short name T242
Test name
Test status
Simulation time 8831720406 ps
CPU time 114.33 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:46:04 PM PST 24
Peak memory 199536 kb
Host smart-267c5edb-29d3-4ca8-8c56-da0e6eeba699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544500028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3544500028
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3063133749
Short name T206
Test name
Test status
Simulation time 561152499 ps
CPU time 4.24 seconds
Started Feb 28 04:44:09 PM PST 24
Finished Feb 28 04:44:13 PM PST 24
Peak memory 199468 kb
Host smart-a7b6a3e0-c41e-4f62-b5f9-8300ea315210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063133749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3063133749
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2748654487
Short name T487
Test name
Test status
Simulation time 3417317375 ps
CPU time 29.4 seconds
Started Feb 28 04:44:13 PM PST 24
Finished Feb 28 04:44:43 PM PST 24
Peak memory 215936 kb
Host smart-5ffba4f5-c916-4c08-b13d-2c6217446ab6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748654487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2748654487
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2753359686
Short name T156
Test name
Test status
Simulation time 46709536 ps
CPU time 1.03 seconds
Started Feb 28 04:44:15 PM PST 24
Finished Feb 28 04:44:16 PM PST 24
Peak memory 197304 kb
Host smart-29d8a24c-b688-49f0-9b5c-9343ae73c98e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753359686 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2753359686
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3107729697
Short name T142
Test name
Test status
Simulation time 6838250299 ps
CPU time 359.36 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:50:16 PM PST 24
Peak memory 199388 kb
Host smart-88636f0b-30f4-4b70-a8d8-bb51dcc28a92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107729697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.3107729697
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3449821143
Short name T205
Test name
Test status
Simulation time 5913850887 ps
CPU time 74.42 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:45:31 PM PST 24
Peak memory 199284 kb
Host smart-7fba2451-4fa1-40af-a031-f38636a65a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449821143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3449821143
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.568741901
Short name T362
Test name
Test status
Simulation time 23935297 ps
CPU time 0.56 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:44:18 PM PST 24
Peak memory 193900 kb
Host smart-e8396a94-88d1-4f14-b016-a9694f67b5f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568741901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.568741901
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.178130442
Short name T347
Test name
Test status
Simulation time 1170518537 ps
CPU time 18.2 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 209488 kb
Host smart-18ceb9f0-6d34-4fa7-9822-8b54b9da77e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178130442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.178130442
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3083505942
Short name T585
Test name
Test status
Simulation time 12362245844 ps
CPU time 22.87 seconds
Started Feb 28 04:44:12 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 199452 kb
Host smart-15a94bfa-6df6-4878-a7ab-bedd749fa0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083505942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3083505942
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1194235476
Short name T259
Test name
Test status
Simulation time 260055486 ps
CPU time 14.79 seconds
Started Feb 28 04:44:15 PM PST 24
Finished Feb 28 04:44:30 PM PST 24
Peak memory 199276 kb
Host smart-e8c673ee-3eb6-4e7d-9f99-df4c39b6e5fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194235476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1194235476
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3214431766
Short name T294
Test name
Test status
Simulation time 25194866675 ps
CPU time 207.56 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:47:43 PM PST 24
Peak memory 199516 kb
Host smart-f7f26eeb-bcf0-4a1e-9d8b-3942f1c6d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214431766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3214431766
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3597600699
Short name T299
Test name
Test status
Simulation time 12332495598 ps
CPU time 77.19 seconds
Started Feb 28 04:44:13 PM PST 24
Finished Feb 28 04:45:30 PM PST 24
Peak memory 199508 kb
Host smart-5f20688b-4d1f-4bac-8dd5-ad3a6a0ed2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597600699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3597600699
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3120283077
Short name T215
Test name
Test status
Simulation time 500236635 ps
CPU time 1.81 seconds
Started Feb 28 04:44:14 PM PST 24
Finished Feb 28 04:44:16 PM PST 24
Peak memory 199456 kb
Host smart-6708a574-95f5-417e-b20d-3153ba9074c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120283077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3120283077
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2001753708
Short name T16
Test name
Test status
Simulation time 15024654653 ps
CPU time 381 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:50:37 PM PST 24
Peak memory 199564 kb
Host smart-e2061116-7de7-48b4-aac7-31d8bdfffbf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001753708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2001753708
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1581153142
Short name T140
Test name
Test status
Simulation time 50924877 ps
CPU time 0.97 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:44:17 PM PST 24
Peak memory 197412 kb
Host smart-bf045951-b656-46a7-a1f9-8504e7340b91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581153142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1581153142
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3948796637
Short name T405
Test name
Test status
Simulation time 14027029570 ps
CPU time 373.6 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:50:30 PM PST 24
Peak memory 199500 kb
Host smart-585e5feb-c5c7-4bf2-9f5c-1252713e8fe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948796637 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3948796637
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.274550588
Short name T346
Test name
Test status
Simulation time 655778798 ps
CPU time 12.11 seconds
Started Feb 28 04:44:15 PM PST 24
Finished Feb 28 04:44:27 PM PST 24
Peak memory 199504 kb
Host smart-52ed3230-d088-4b83-8bb3-09efbf65aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274550588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.274550588
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.452505440
Short name T384
Test name
Test status
Simulation time 20823900 ps
CPU time 0.58 seconds
Started Feb 28 04:44:19 PM PST 24
Finished Feb 28 04:44:20 PM PST 24
Peak memory 194068 kb
Host smart-9f1de14d-2e7a-4481-8fbd-bbe10ee6b13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452505440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.452505440
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4216402726
Short name T50
Test name
Test status
Simulation time 1557055335 ps
CPU time 27.68 seconds
Started Feb 28 04:44:20 PM PST 24
Finished Feb 28 04:44:48 PM PST 24
Peak memory 224996 kb
Host smart-0f1dcc35-3338-4980-a127-2269a7dca1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216402726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4216402726
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.870172305
Short name T275
Test name
Test status
Simulation time 2503702046 ps
CPU time 35.23 seconds
Started Feb 28 04:44:19 PM PST 24
Finished Feb 28 04:44:54 PM PST 24
Peak memory 199488 kb
Host smart-ea888716-297c-4b7d-8ada-42cb904e1cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870172305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.870172305
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2392801684
Short name T197
Test name
Test status
Simulation time 1414690028 ps
CPU time 37.83 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:44:55 PM PST 24
Peak memory 199420 kb
Host smart-67a01ab4-edbd-4e3f-80ac-b602291ec268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392801684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2392801684
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2472370980
Short name T6
Test name
Test status
Simulation time 38519123722 ps
CPU time 73.43 seconds
Started Feb 28 04:44:16 PM PST 24
Finished Feb 28 04:45:29 PM PST 24
Peak memory 199488 kb
Host smart-9dd162db-5289-40e6-8419-c5ad1149fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472370980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2472370980
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1311868714
Short name T100
Test name
Test status
Simulation time 45801474957 ps
CPU time 102.04 seconds
Started Feb 28 04:44:17 PM PST 24
Finished Feb 28 04:45:59 PM PST 24
Peak memory 199440 kb
Host smart-96616421-c7ad-4160-a946-f2f1eae690ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311868714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1311868714
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1339059175
Short name T234
Test name
Test status
Simulation time 1374666142 ps
CPU time 3.97 seconds
Started Feb 28 04:44:20 PM PST 24
Finished Feb 28 04:44:24 PM PST 24
Peak memory 199432 kb
Host smart-ae76cd70-c990-407a-963a-739fce5c0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339059175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1339059175
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.697299297
Short name T70
Test name
Test status
Simulation time 56452414496 ps
CPU time 747.21 seconds
Started Feb 28 04:44:18 PM PST 24
Finished Feb 28 04:56:46 PM PST 24
Peak memory 234024 kb
Host smart-93745608-cab8-450e-8b87-96ac36a3302b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697299297 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.697299297
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1920034107
Short name T290
Test name
Test status
Simulation time 67416995 ps
CPU time 1.25 seconds
Started Feb 28 04:44:21 PM PST 24
Finished Feb 28 04:44:22 PM PST 24
Peak memory 199016 kb
Host smart-e57d1257-325b-48e4-8457-b445adfd1564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920034107 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1920034107
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1314896619
Short name T46
Test name
Test status
Simulation time 25820616015 ps
CPU time 398.91 seconds
Started Feb 28 04:44:21 PM PST 24
Finished Feb 28 04:51:00 PM PST 24
Peak memory 199368 kb
Host smart-0b990a70-51b0-4539-9839-fd8b84b5a3ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314896619 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.1314896619
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3672759280
Short name T195
Test name
Test status
Simulation time 21383250467 ps
CPU time 74.93 seconds
Started Feb 28 04:44:19 PM PST 24
Finished Feb 28 04:45:34 PM PST 24
Peak memory 199444 kb
Host smart-86e62079-90cf-4926-b9ec-a50c0d1a608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672759280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3672759280
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.716975691
Short name T238
Test name
Test status
Simulation time 38232941 ps
CPU time 0.55 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 193620 kb
Host smart-5ff0879e-ac6d-4202-b2b0-a2b147bf93d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716975691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.716975691
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.263603359
Short name T413
Test name
Test status
Simulation time 613719785 ps
CPU time 9.67 seconds
Started Feb 28 04:44:23 PM PST 24
Finished Feb 28 04:44:33 PM PST 24
Peak memory 199472 kb
Host smart-0459edd3-9397-4e73-ac5f-a978e0a9d0f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263603359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.263603359
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1761219546
Short name T258
Test name
Test status
Simulation time 1278887453 ps
CPU time 23.98 seconds
Started Feb 28 04:44:25 PM PST 24
Finished Feb 28 04:44:49 PM PST 24
Peak memory 199436 kb
Host smart-434517d6-cf8a-4e7e-b97e-1dfb7d7be9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761219546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1761219546
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2137831774
Short name T111
Test name
Test status
Simulation time 2996067343 ps
CPU time 86.17 seconds
Started Feb 28 04:44:26 PM PST 24
Finished Feb 28 04:45:52 PM PST 24
Peak memory 199528 kb
Host smart-6d34405f-6db7-44eb-8e89-3588855d6a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137831774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2137831774
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1242207416
Short name T567
Test name
Test status
Simulation time 9739973714 ps
CPU time 102.13 seconds
Started Feb 28 04:44:26 PM PST 24
Finished Feb 28 04:46:08 PM PST 24
Peak memory 199508 kb
Host smart-da1cbf71-db33-4a71-84b8-9b4345815789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242207416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1242207416
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_smoke.2957773256
Short name T465
Test name
Test status
Simulation time 188011142 ps
CPU time 2.79 seconds
Started Feb 28 04:44:27 PM PST 24
Finished Feb 28 04:44:30 PM PST 24
Peak memory 199276 kb
Host smart-98fff131-5693-4c8c-bf9e-a945a7b10b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957773256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2957773256
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3998972197
Short name T106
Test name
Test status
Simulation time 58441762533 ps
CPU time 662.18 seconds
Started Feb 28 04:44:24 PM PST 24
Finished Feb 28 04:55:26 PM PST 24
Peak memory 226124 kb
Host smart-ebc951c9-4008-48cc-97ad-938ca1b30c3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998972197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3998972197
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.4178252397
Short name T597
Test name
Test status
Simulation time 96725257 ps
CPU time 0.85 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:33 PM PST 24
Peak memory 197136 kb
Host smart-e18f6303-11c2-433f-a1e6-c13b887345e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178252397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.4178252397
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.818999875
Short name T284
Test name
Test status
Simulation time 67208559990 ps
CPU time 447.23 seconds
Started Feb 28 04:44:27 PM PST 24
Finished Feb 28 04:51:54 PM PST 24
Peak memory 199468 kb
Host smart-91855e28-c0e9-475d-a5f5-b5b3b4e5a679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818999875 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_sha_vectors.818999875
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3595584850
Short name T394
Test name
Test status
Simulation time 26968340001 ps
CPU time 68.38 seconds
Started Feb 28 04:44:30 PM PST 24
Finished Feb 28 04:45:39 PM PST 24
Peak memory 199560 kb
Host smart-68709a6b-d558-4d19-a395-64946abc18d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595584850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3595584850
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.378016899
Short name T36
Test name
Test status
Simulation time 15714631 ps
CPU time 0.57 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 193844 kb
Host smart-996bd85b-5c1a-4c20-b5fc-e2834c9cced4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378016899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.378016899
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3072635626
Short name T129
Test name
Test status
Simulation time 807508324 ps
CPU time 31.35 seconds
Started Feb 28 04:44:27 PM PST 24
Finished Feb 28 04:44:59 PM PST 24
Peak memory 233236 kb
Host smart-6474df20-1794-409d-92cf-506bc974ccf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072635626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3072635626
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1446839977
Short name T160
Test name
Test status
Simulation time 1486382807 ps
CPU time 20.54 seconds
Started Feb 28 04:44:28 PM PST 24
Finished Feb 28 04:44:49 PM PST 24
Peak memory 199424 kb
Host smart-3dc63f3d-bc01-4a94-941e-cd8ebabc5089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446839977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1446839977
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.307319585
Short name T270
Test name
Test status
Simulation time 3768710194 ps
CPU time 104.76 seconds
Started Feb 28 04:44:28 PM PST 24
Finished Feb 28 04:46:13 PM PST 24
Peak memory 199532 kb
Host smart-35343a33-4160-42a0-b667-4b896d34f03e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307319585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.307319585
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2476547873
Short name T584
Test name
Test status
Simulation time 2352755360 ps
CPU time 38.05 seconds
Started Feb 28 04:44:27 PM PST 24
Finished Feb 28 04:45:06 PM PST 24
Peak memory 199548 kb
Host smart-71f0b6f2-f7ef-4c0e-a08a-3045eef6f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476547873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2476547873
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4284575308
Short name T422
Test name
Test status
Simulation time 15686962989 ps
CPU time 98.76 seconds
Started Feb 28 04:44:28 PM PST 24
Finished Feb 28 04:46:07 PM PST 24
Peak memory 199496 kb
Host smart-a1010531-bcb9-4d91-a725-fa88a8faa2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284575308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4284575308
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.978141742
Short name T484
Test name
Test status
Simulation time 30796401 ps
CPU time 0.71 seconds
Started Feb 28 04:44:23 PM PST 24
Finished Feb 28 04:44:25 PM PST 24
Peak memory 195480 kb
Host smart-d79adda6-e031-4f44-87bd-7a41c37f2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978141742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.978141742
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1683616320
Short name T110
Test name
Test status
Simulation time 72425206811 ps
CPU time 298.31 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:49:29 PM PST 24
Peak memory 199504 kb
Host smart-863c263c-1510-4556-90ea-ebb130b101ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683616320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1683616320
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2247513144
Short name T468
Test name
Test status
Simulation time 32222631 ps
CPU time 1.08 seconds
Started Feb 28 04:44:27 PM PST 24
Finished Feb 28 04:44:29 PM PST 24
Peak memory 198332 kb
Host smart-9982690a-1744-4e6b-826e-03d21cea40de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247513144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2247513144
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.472099216
Short name T403
Test name
Test status
Simulation time 15294992094 ps
CPU time 398.15 seconds
Started Feb 28 04:44:28 PM PST 24
Finished Feb 28 04:51:07 PM PST 24
Peak memory 199392 kb
Host smart-a0fc76c8-cb12-4fa5-bd2b-7be02ad70a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472099216 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.472099216
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.627240260
Short name T171
Test name
Test status
Simulation time 1731362535 ps
CPU time 22.93 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:55 PM PST 24
Peak memory 199456 kb
Host smart-36510509-b401-4151-88c1-073005574304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627240260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.627240260
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3245839599
Short name T298
Test name
Test status
Simulation time 36924829 ps
CPU time 0.58 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:44:36 PM PST 24
Peak memory 194080 kb
Host smart-99ce527d-2cfd-4106-97c4-129a81f0ded5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245839599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3245839599
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1939175738
Short name T107
Test name
Test status
Simulation time 1508204727 ps
CPU time 57.35 seconds
Started Feb 28 04:44:29 PM PST 24
Finished Feb 28 04:45:26 PM PST 24
Peak memory 229200 kb
Host smart-f10a0964-c287-4038-a676-adb6b611fb29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939175738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1939175738
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3298858082
Short name T212
Test name
Test status
Simulation time 52763187 ps
CPU time 2.27 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:34 PM PST 24
Peak memory 199364 kb
Host smart-4096f339-35fb-44a2-a957-a39e7f4a8820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298858082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3298858082
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3954854843
Short name T469
Test name
Test status
Simulation time 1251161104 ps
CPU time 69.24 seconds
Started Feb 28 04:44:30 PM PST 24
Finished Feb 28 04:45:40 PM PST 24
Peak memory 199480 kb
Host smart-4b6c985c-1816-46e4-9f16-af12736c72f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954854843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3954854843
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2897888164
Short name T374
Test name
Test status
Simulation time 7418169695 ps
CPU time 84.13 seconds
Started Feb 28 04:44:29 PM PST 24
Finished Feb 28 04:45:54 PM PST 24
Peak memory 199512 kb
Host smart-d3677e1a-3555-4364-befb-bba12ad892f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897888164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2897888164
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.488819986
Short name T228
Test name
Test status
Simulation time 2986232971 ps
CPU time 12.7 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:44:45 PM PST 24
Peak memory 199544 kb
Host smart-cd53af63-d7cd-4058-ac9d-d638dee67cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488819986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.488819986
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3287040747
Short name T342
Test name
Test status
Simulation time 175866273 ps
CPU time 2.17 seconds
Started Feb 28 04:44:30 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 199368 kb
Host smart-b9c8e299-a2b8-45b0-8bab-df2e3cff821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287040747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3287040747
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2166089377
Short name T531
Test name
Test status
Simulation time 22623785541 ps
CPU time 36.98 seconds
Started Feb 28 04:44:32 PM PST 24
Finished Feb 28 04:45:09 PM PST 24
Peak memory 215896 kb
Host smart-54b3d359-abe7-42c0-b1af-6384bb2aad0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166089377 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2166089377
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.251101049
Short name T485
Test name
Test status
Simulation time 105994053 ps
CPU time 1.14 seconds
Started Feb 28 04:44:30 PM PST 24
Finished Feb 28 04:44:32 PM PST 24
Peak memory 197944 kb
Host smart-be61166b-dd5b-494e-afde-bfaec88bf1d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251101049 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.251101049
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.601813297
Short name T349
Test name
Test status
Simulation time 28141988954 ps
CPU time 456.72 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:52:08 PM PST 24
Peak memory 199340 kb
Host smart-5552ebaa-540e-4d48-ba2a-1718b3e0e11a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601813297 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.hmac_test_sha_vectors.601813297
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2465905155
Short name T301
Test name
Test status
Simulation time 6987095111 ps
CPU time 24.66 seconds
Started Feb 28 04:44:28 PM PST 24
Finished Feb 28 04:44:53 PM PST 24
Peak memory 199504 kb
Host smart-46e26363-6348-491b-ad6b-5500d4217522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465905155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2465905155
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3300484298
Short name T563
Test name
Test status
Simulation time 37488028 ps
CPU time 0.57 seconds
Started Feb 28 04:44:34 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 193800 kb
Host smart-c882c36f-f470-4acc-85b8-4f2bd5347fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300484298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3300484298
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3673563077
Short name T446
Test name
Test status
Simulation time 2434575346 ps
CPU time 22.33 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:45:02 PM PST 24
Peak memory 221028 kb
Host smart-28164ef1-49a5-4d74-90d2-a4e295a51543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673563077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3673563077
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1555037376
Short name T66
Test name
Test status
Simulation time 2829568116 ps
CPU time 33.8 seconds
Started Feb 28 04:44:31 PM PST 24
Finished Feb 28 04:45:05 PM PST 24
Peak memory 199560 kb
Host smart-01f8fe04-d123-47b4-b914-57caf1b049e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555037376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1555037376
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3451840086
Short name T102
Test name
Test status
Simulation time 2895158685 ps
CPU time 74.73 seconds
Started Feb 28 04:44:37 PM PST 24
Finished Feb 28 04:45:52 PM PST 24
Peak memory 199540 kb
Host smart-cc9dea07-ac45-4189-9911-302c4498b66d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451840086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3451840086
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2559510801
Short name T600
Test name
Test status
Simulation time 13274359858 ps
CPU time 163.8 seconds
Started Feb 28 04:44:37 PM PST 24
Finished Feb 28 04:47:21 PM PST 24
Peak memory 199504 kb
Host smart-8a932e7c-5b3c-42e3-9873-745c6e75563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559510801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2559510801
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1841433399
Short name T515
Test name
Test status
Simulation time 1381636711 ps
CPU time 10.15 seconds
Started Feb 28 04:44:37 PM PST 24
Finished Feb 28 04:44:47 PM PST 24
Peak memory 199460 kb
Host smart-4931011d-83d6-4ab2-96b8-1c451b820b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841433399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1841433399
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.708423223
Short name T175
Test name
Test status
Simulation time 369502812 ps
CPU time 1.4 seconds
Started Feb 28 04:44:32 PM PST 24
Finished Feb 28 04:44:34 PM PST 24
Peak memory 199436 kb
Host smart-bc06275b-771c-4972-b8cc-93fd088028c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708423223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.708423223
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.154574888
Short name T220
Test name
Test status
Simulation time 148639885183 ps
CPU time 600.21 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:54:36 PM PST 24
Peak memory 199560 kb
Host smart-718f5005-8968-4150-9584-1cc7386be19a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154574888 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.154574888
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3141513610
Short name T158
Test name
Test status
Simulation time 746439797 ps
CPU time 0.96 seconds
Started Feb 28 04:44:34 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 198096 kb
Host smart-6ee83e65-2735-4da2-9140-b39b838cb246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141513610 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3141513610
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2908691289
Short name T545
Test name
Test status
Simulation time 139342082637 ps
CPU time 446.29 seconds
Started Feb 28 04:44:37 PM PST 24
Finished Feb 28 04:52:03 PM PST 24
Peak memory 199476 kb
Host smart-c54031bd-2700-4d20-8c2a-885ca0c49f98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908691289 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2908691289
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1296768366
Short name T481
Test name
Test status
Simulation time 680940559 ps
CPU time 29.07 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:45:09 PM PST 24
Peak memory 199412 kb
Host smart-c9f16ded-520c-48d1-96a7-f3222578cdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296768366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1296768366
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1507478965
Short name T13
Test name
Test status
Simulation time 23424747 ps
CPU time 0.57 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:44:36 PM PST 24
Peak memory 193812 kb
Host smart-0f40c69d-0fd5-4204-ace3-b9e8df84f310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507478965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1507478965
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2698119470
Short name T180
Test name
Test status
Simulation time 3856329396 ps
CPU time 31.71 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:45:07 PM PST 24
Peak memory 207740 kb
Host smart-c315c1e1-6a8a-46ec-b8a1-71bd3a0bed67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698119470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2698119470
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.422570129
Short name T217
Test name
Test status
Simulation time 410207068 ps
CPU time 9.76 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:44:49 PM PST 24
Peak memory 199476 kb
Host smart-a70480a3-1ff3-4e42-ac9d-b473787a8fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422570129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.422570129
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1851329739
Short name T439
Test name
Test status
Simulation time 3482443809 ps
CPU time 29.31 seconds
Started Feb 28 04:44:34 PM PST 24
Finished Feb 28 04:45:03 PM PST 24
Peak memory 199556 kb
Host smart-c03aa8a2-d554-4c3b-8069-e8f91a2e506f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851329739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1851329739
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.176445194
Short name T566
Test name
Test status
Simulation time 2660725386 ps
CPU time 151.08 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:47:10 PM PST 24
Peak memory 199656 kb
Host smart-b1ee0b8a-72c7-4f90-9eb0-72532fb1ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176445194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.176445194
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1140791368
Short name T323
Test name
Test status
Simulation time 86783349056 ps
CPU time 95.15 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:46:10 PM PST 24
Peak memory 199568 kb
Host smart-dd94d2f8-dd10-4147-925d-94e196b83a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140791368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1140791368
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.800113840
Short name T542
Test name
Test status
Simulation time 1307887908 ps
CPU time 2.08 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:44:42 PM PST 24
Peak memory 199484 kb
Host smart-d5d22aa2-a4de-411b-b5b8-0141035b3529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800113840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.800113840
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1925008774
Short name T376
Test name
Test status
Simulation time 111318786784 ps
CPU time 492.47 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:52:51 PM PST 24
Peak memory 247852 kb
Host smart-4b13ed70-a549-49cc-9981-6367f868783e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925008774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1925008774
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.253363984
Short name T423
Test name
Test status
Simulation time 47501147 ps
CPU time 1.02 seconds
Started Feb 28 04:44:38 PM PST 24
Finished Feb 28 04:44:39 PM PST 24
Peak memory 196888 kb
Host smart-09665c9a-781c-4669-b27b-dd7de5012a2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253363984 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_hmac_vectors.253363984
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3076552169
Short name T339
Test name
Test status
Simulation time 40733445202 ps
CPU time 470.01 seconds
Started Feb 28 04:44:36 PM PST 24
Finished Feb 28 04:52:26 PM PST 24
Peak memory 199428 kb
Host smart-0f749700-0aec-4d38-bcb5-ecb70ccf830f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076552169 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.3076552169
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3211935511
Short name T480
Test name
Test status
Simulation time 3783485007 ps
CPU time 67.44 seconds
Started Feb 28 04:44:36 PM PST 24
Finished Feb 28 04:45:43 PM PST 24
Peak memory 199504 kb
Host smart-820868c4-2602-45d5-abb6-a92eda89d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211935511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3211935511
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1678002318
Short name T295
Test name
Test status
Simulation time 14255680 ps
CPU time 0.58 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:42:54 PM PST 24
Peak memory 193748 kb
Host smart-509deecb-5a19-44aa-955b-1a8285ae8144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678002318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1678002318
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.884869337
Short name T381
Test name
Test status
Simulation time 1428361284 ps
CPU time 19.65 seconds
Started Feb 28 04:42:49 PM PST 24
Finished Feb 28 04:43:09 PM PST 24
Peak memory 215400 kb
Host smart-cb8236b4-2656-42c9-bb18-e5cf3fa45f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884869337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.884869337
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2310281187
Short name T450
Test name
Test status
Simulation time 3742885124 ps
CPU time 6.2 seconds
Started Feb 28 04:42:52 PM PST 24
Finished Feb 28 04:42:58 PM PST 24
Peak memory 199356 kb
Host smart-43119565-cd96-4bd2-b43a-a0a3c44eb1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310281187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2310281187
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3894799419
Short name T575
Test name
Test status
Simulation time 3100440923 ps
CPU time 36.69 seconds
Started Feb 28 04:42:54 PM PST 24
Finished Feb 28 04:43:31 PM PST 24
Peak memory 199256 kb
Host smart-3a3df6e2-ed7c-454f-8623-ed3aad96960f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894799419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3894799419
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2842461638
Short name T28
Test name
Test status
Simulation time 13981636931 ps
CPU time 177.57 seconds
Started Feb 28 04:42:51 PM PST 24
Finished Feb 28 04:45:48 PM PST 24
Peak memory 199516 kb
Host smart-e2c031c2-34db-446c-b385-e8bbdb9d7aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842461638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2842461638
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3387337418
Short name T282
Test name
Test status
Simulation time 2414366956 ps
CPU time 32.38 seconds
Started Feb 28 04:42:55 PM PST 24
Finished Feb 28 04:43:27 PM PST 24
Peak memory 199372 kb
Host smart-57836938-6cd9-43d9-810e-48665ea45556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387337418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3387337418
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2938958556
Short name T27
Test name
Test status
Simulation time 378682703 ps
CPU time 0.94 seconds
Started Feb 28 04:42:52 PM PST 24
Finished Feb 28 04:42:53 PM PST 24
Peak memory 217820 kb
Host smart-5e56b30e-4eb9-43c3-ae79-59f9159538dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938958556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2938958556
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.100892750
Short name T378
Test name
Test status
Simulation time 564885580 ps
CPU time 3.55 seconds
Started Feb 28 04:42:49 PM PST 24
Finished Feb 28 04:42:53 PM PST 24
Peak memory 199360 kb
Host smart-ff05b5c0-a464-42fa-82bc-12d749ac26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100892750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.100892750
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3026494188
Short name T255
Test name
Test status
Simulation time 71250595690 ps
CPU time 726.12 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:55:00 PM PST 24
Peak memory 199564 kb
Host smart-c859bf2c-f681-4925-95c2-a153e22ed1b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026494188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3026494188
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1697677
Short name T330
Test name
Test status
Simulation time 63693317 ps
CPU time 1.08 seconds
Started Feb 28 04:42:55 PM PST 24
Finished Feb 28 04:42:56 PM PST 24
Peak memory 197056 kb
Host smart-85091c59-f3c0-4565-9e13-c570b83aaff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697677 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.hmac_test_hmac_vectors.1697677
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.381657432
Short name T256
Test name
Test status
Simulation time 7475449611 ps
CPU time 390.53 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:49:24 PM PST 24
Peak memory 199440 kb
Host smart-437b97e6-b964-4217-b5be-31ae396a2117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381657432 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.hmac_test_sha_vectors.381657432
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.862970448
Short name T411
Test name
Test status
Simulation time 4436330070 ps
CPU time 89.51 seconds
Started Feb 28 04:42:50 PM PST 24
Finished Feb 28 04:44:20 PM PST 24
Peak memory 199636 kb
Host smart-adc2290c-dd20-4513-bd4d-84d372e6c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862970448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.862970448
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1670811278
Short name T476
Test name
Test status
Simulation time 12666809 ps
CPU time 0.58 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:44:40 PM PST 24
Peak memory 193732 kb
Host smart-83f3f605-0f1c-4e4d-9a90-67ab780416c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670811278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1670811278
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2286895503
Short name T442
Test name
Test status
Simulation time 1265398098 ps
CPU time 47.29 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:45:30 PM PST 24
Peak memory 240372 kb
Host smart-5e699729-2664-4386-9b02-8710b4a94383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286895503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2286895503
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2537772168
Short name T274
Test name
Test status
Simulation time 118489952 ps
CPU time 2.64 seconds
Started Feb 28 04:44:38 PM PST 24
Finished Feb 28 04:44:41 PM PST 24
Peak memory 199304 kb
Host smart-08a86bca-fbfa-45c9-9b02-82170bba066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537772168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2537772168
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4104907435
Short name T18
Test name
Test status
Simulation time 2779883478 ps
CPU time 36.08 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:45:20 PM PST 24
Peak memory 199516 kb
Host smart-92cb5a34-e83e-445b-9895-1fb7d6818de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104907435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4104907435
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2636877027
Short name T288
Test name
Test status
Simulation time 2835610994 ps
CPU time 149.46 seconds
Started Feb 28 04:44:41 PM PST 24
Finished Feb 28 04:47:10 PM PST 24
Peak memory 199568 kb
Host smart-3c6e0608-fa75-4194-be91-edf03cff2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636877027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2636877027
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2091859315
Short name T426
Test name
Test status
Simulation time 702737391 ps
CPU time 8.93 seconds
Started Feb 28 04:44:35 PM PST 24
Finished Feb 28 04:44:45 PM PST 24
Peak memory 199608 kb
Host smart-798700f9-5dd3-4e76-8e59-354fe94c6a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091859315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2091859315
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1511426167
Short name T182
Test name
Test status
Simulation time 36331295 ps
CPU time 1.18 seconds
Started Feb 28 04:44:37 PM PST 24
Finished Feb 28 04:44:38 PM PST 24
Peak memory 199380 kb
Host smart-ebd295bd-de16-41c1-9b79-8969bc4a46e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511426167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1511426167
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.397555018
Short name T337
Test name
Test status
Simulation time 200272580143 ps
CPU time 687.77 seconds
Started Feb 28 04:44:42 PM PST 24
Finished Feb 28 04:56:10 PM PST 24
Peak memory 199496 kb
Host smart-4d9c3d14-62dc-4737-ad6c-a9ef48535c70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397555018 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.397555018
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.324080454
Short name T424
Test name
Test status
Simulation time 66236840 ps
CPU time 1.22 seconds
Started Feb 28 04:44:41 PM PST 24
Finished Feb 28 04:44:43 PM PST 24
Peak memory 198328 kb
Host smart-b18b7da1-58e8-4388-a141-4d64f109203a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324080454 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.324080454
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.630291788
Short name T114
Test name
Test status
Simulation time 3253095673 ps
CPU time 55.91 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:45:35 PM PST 24
Peak memory 199520 kb
Host smart-c98390e8-99a8-4542-893e-5d2154e396fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630291788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.630291788
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1030878166
Short name T486
Test name
Test status
Simulation time 14122897 ps
CPU time 0.57 seconds
Started Feb 28 04:44:47 PM PST 24
Finished Feb 28 04:44:48 PM PST 24
Peak memory 193240 kb
Host smart-25eebd75-4662-46bc-aeb7-720e33f7364e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030878166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1030878166
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2191071600
Short name T428
Test name
Test status
Simulation time 237482967 ps
CPU time 7.3 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:44:50 PM PST 24
Peak memory 199452 kb
Host smart-e5a48eaf-3961-4137-9bbe-368736a1d270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191071600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2191071600
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2298058800
Short name T448
Test name
Test status
Simulation time 2665315572 ps
CPU time 37.82 seconds
Started Feb 28 04:44:40 PM PST 24
Finished Feb 28 04:45:18 PM PST 24
Peak memory 199344 kb
Host smart-507a56f6-ab6c-4d7e-b589-6a30141cc346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298058800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2298058800
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3827249594
Short name T112
Test name
Test status
Simulation time 1289962912 ps
CPU time 69.16 seconds
Started Feb 28 04:44:42 PM PST 24
Finished Feb 28 04:45:52 PM PST 24
Peak memory 199392 kb
Host smart-c40f14da-30fa-400a-aaa2-88e108f34c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827249594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3827249594
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1783632666
Short name T177
Test name
Test status
Simulation time 2149636893 ps
CPU time 105.47 seconds
Started Feb 28 04:44:41 PM PST 24
Finished Feb 28 04:46:27 PM PST 24
Peak memory 199456 kb
Host smart-82344970-c71f-4b92-b22f-7e0956fe83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783632666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1783632666
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.647035171
Short name T154
Test name
Test status
Simulation time 6888346990 ps
CPU time 45.73 seconds
Started Feb 28 04:44:39 PM PST 24
Finished Feb 28 04:45:26 PM PST 24
Peak memory 199564 kb
Host smart-d5779c0e-a232-44ba-9038-fc401a8ab237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647035171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.647035171
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1123786664
Short name T209
Test name
Test status
Simulation time 289802083 ps
CPU time 3.42 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:44:47 PM PST 24
Peak memory 199168 kb
Host smart-f61456ec-9784-41c8-bd13-48272c1b2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123786664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1123786664
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3991426964
Short name T356
Test name
Test status
Simulation time 74926380419 ps
CPU time 994.36 seconds
Started Feb 28 04:44:42 PM PST 24
Finished Feb 28 05:01:17 PM PST 24
Peak memory 224168 kb
Host smart-c14c4b3e-e0e8-4019-b2a9-65ee0ed732b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991426964 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3991426964
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3914561621
Short name T457
Test name
Test status
Simulation time 379909595 ps
CPU time 1.21 seconds
Started Feb 28 04:44:45 PM PST 24
Finished Feb 28 04:44:46 PM PST 24
Peak memory 198120 kb
Host smart-8c4ab890-f93d-4b4b-8250-22c00045c99c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914561621 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3914561621
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.4084191939
Short name T287
Test name
Test status
Simulation time 36355064980 ps
CPU time 412.88 seconds
Started Feb 28 04:44:38 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 199436 kb
Host smart-476b9a42-1c62-4de9-a7eb-c59f94ac76e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084191939 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.4084191939
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3656808161
Short name T276
Test name
Test status
Simulation time 4709535186 ps
CPU time 8.34 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:44:51 PM PST 24
Peak memory 199540 kb
Host smart-1bba1769-f496-4a2a-bb09-a77302d1f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656808161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3656808161
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1150333368
Short name T371
Test name
Test status
Simulation time 12756144 ps
CPU time 0.61 seconds
Started Feb 28 04:44:47 PM PST 24
Finished Feb 28 04:44:47 PM PST 24
Peak memory 193836 kb
Host smart-b648a727-b025-4a8a-85a7-6cfa1d5a421a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150333368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1150333368
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2734610534
Short name T354
Test name
Test status
Simulation time 5558328144 ps
CPU time 51.41 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:45:35 PM PST 24
Peak memory 232112 kb
Host smart-685e6dc1-7baa-458e-917c-d29395ad067c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734610534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2734610534
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1448656899
Short name T547
Test name
Test status
Simulation time 2420727440 ps
CPU time 59.4 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:45:43 PM PST 24
Peak memory 199428 kb
Host smart-c5570223-43a2-4283-8b72-35b6bf08972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448656899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1448656899
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4107339959
Short name T202
Test name
Test status
Simulation time 548951698 ps
CPU time 28.59 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:45:12 PM PST 24
Peak memory 199492 kb
Host smart-74600cf9-6bea-4636-b5ed-2086776ebfba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107339959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4107339959
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3536457393
Short name T35
Test name
Test status
Simulation time 16524703136 ps
CPU time 53.75 seconds
Started Feb 28 04:44:47 PM PST 24
Finished Feb 28 04:45:41 PM PST 24
Peak memory 198984 kb
Host smart-8617a6e5-c25d-4913-926d-8c51410e9f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536457393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3536457393
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3879240847
Short name T397
Test name
Test status
Simulation time 242337947 ps
CPU time 1.8 seconds
Started Feb 28 04:44:43 PM PST 24
Finished Feb 28 04:44:45 PM PST 24
Peak memory 199384 kb
Host smart-f2852cd7-db4f-4198-8442-70f7764ae2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879240847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3879240847
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3338923489
Short name T495
Test name
Test status
Simulation time 16923820583 ps
CPU time 65.78 seconds
Started Feb 28 04:44:46 PM PST 24
Finished Feb 28 04:45:52 PM PST 24
Peak memory 199572 kb
Host smart-d171f52b-1455-481a-b399-3e8114c6c95a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338923489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3338923489
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3666728338
Short name T529
Test name
Test status
Simulation time 240747409 ps
CPU time 1.18 seconds
Started Feb 28 04:44:47 PM PST 24
Finished Feb 28 04:44:48 PM PST 24
Peak memory 198248 kb
Host smart-7fb267f8-e853-4d1e-8b76-e52c1946855a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666728338 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3666728338
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2253780230
Short name T571
Test name
Test status
Simulation time 105946528583 ps
CPU time 494.77 seconds
Started Feb 28 04:44:46 PM PST 24
Finished Feb 28 04:53:01 PM PST 24
Peak memory 199440 kb
Host smart-947d81c7-f4c4-44c1-b16e-3bc7714390eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253780230 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2253780230
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3016243031
Short name T482
Test name
Test status
Simulation time 1564368163 ps
CPU time 10.4 seconds
Started Feb 28 04:44:44 PM PST 24
Finished Feb 28 04:44:55 PM PST 24
Peak memory 199464 kb
Host smart-f63b11ad-d430-472f-bf2b-1f8c5ace2b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016243031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3016243031
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1161379892
Short name T222
Test name
Test status
Simulation time 39115175 ps
CPU time 0.55 seconds
Started Feb 28 04:44:49 PM PST 24
Finished Feb 28 04:44:50 PM PST 24
Peak memory 193820 kb
Host smart-dcb7ca76-ea6e-472d-b03a-510f22fc07e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161379892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1161379892
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.871190414
Short name T355
Test name
Test status
Simulation time 5091639576 ps
CPU time 41.03 seconds
Started Feb 28 04:44:46 PM PST 24
Finished Feb 28 04:45:28 PM PST 24
Peak memory 208684 kb
Host smart-7c296d39-5c33-49db-960c-548c4d9386fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871190414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.871190414
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2623352135
Short name T551
Test name
Test status
Simulation time 6561660619 ps
CPU time 74.59 seconds
Started Feb 28 04:44:50 PM PST 24
Finished Feb 28 04:46:04 PM PST 24
Peak memory 199428 kb
Host smart-0ba7a034-de3a-487e-9259-d5d142435d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623352135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2623352135
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.386915431
Short name T513
Test name
Test status
Simulation time 419167198 ps
CPU time 17.86 seconds
Started Feb 28 04:44:49 PM PST 24
Finished Feb 28 04:45:07 PM PST 24
Peak memory 199424 kb
Host smart-7ee5cab5-32eb-414f-8ca7-fe837cbd5b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386915431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.386915431
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3516280088
Short name T501
Test name
Test status
Simulation time 10196044906 ps
CPU time 35.01 seconds
Started Feb 28 04:44:53 PM PST 24
Finished Feb 28 04:45:28 PM PST 24
Peak memory 199472 kb
Host smart-cc2bc66c-9b46-4c2e-be11-f7ae3472c188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516280088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3516280088
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4116119723
Short name T99
Test name
Test status
Simulation time 3398313297 ps
CPU time 68.14 seconds
Started Feb 28 04:44:47 PM PST 24
Finished Feb 28 04:45:55 PM PST 24
Peak memory 199588 kb
Host smart-065801ee-310a-4db5-96df-7b8f5dcc11f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116119723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4116119723
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2756808935
Short name T582
Test name
Test status
Simulation time 129839313 ps
CPU time 1.21 seconds
Started Feb 28 04:44:45 PM PST 24
Finished Feb 28 04:44:47 PM PST 24
Peak memory 198908 kb
Host smart-0f627006-9f9e-4ecf-80f0-9bf1dac19374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756808935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2756808935
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1828177963
Short name T277
Test name
Test status
Simulation time 145287876687 ps
CPU time 1300 seconds
Started Feb 28 04:44:51 PM PST 24
Finished Feb 28 05:06:32 PM PST 24
Peak memory 199588 kb
Host smart-d58fd066-c9b3-49ef-b4b4-df74af5ba4b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828177963 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1828177963
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2522617056
Short name T249
Test name
Test status
Simulation time 42584836 ps
CPU time 1 seconds
Started Feb 28 04:44:53 PM PST 24
Finished Feb 28 04:44:54 PM PST 24
Peak memory 196948 kb
Host smart-dd8277e4-a379-4e06-ab12-744e31e54632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522617056 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2522617056
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1194687181
Short name T598
Test name
Test status
Simulation time 51625471890 ps
CPU time 398.05 seconds
Started Feb 28 04:44:52 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 199472 kb
Host smart-7162b38e-0244-4bf8-b87b-7fff8b37a85c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194687181 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.1194687181
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2239443115
Short name T464
Test name
Test status
Simulation time 3019941328 ps
CPU time 40.11 seconds
Started Feb 28 04:44:49 PM PST 24
Finished Feb 28 04:45:29 PM PST 24
Peak memory 199544 kb
Host smart-64fe40c9-1b5e-4229-92ff-3a5f492076ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239443115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2239443115
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1989236401
Short name T434
Test name
Test status
Simulation time 14718055 ps
CPU time 0.58 seconds
Started Feb 28 04:44:55 PM PST 24
Finished Feb 28 04:44:56 PM PST 24
Peak memory 193728 kb
Host smart-9f9fc098-1d28-4371-869e-76f2e7a10d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989236401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1989236401
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.726994549
Short name T225
Test name
Test status
Simulation time 2210524712 ps
CPU time 51.25 seconds
Started Feb 28 04:44:53 PM PST 24
Finished Feb 28 04:45:45 PM PST 24
Peak memory 223332 kb
Host smart-c4dca343-384c-4087-800a-06edc1b44c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726994549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.726994549
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1644361300
Short name T493
Test name
Test status
Simulation time 79186417287 ps
CPU time 55.89 seconds
Started Feb 28 04:44:54 PM PST 24
Finished Feb 28 04:45:50 PM PST 24
Peak memory 199668 kb
Host smart-7062ea34-8fb4-4700-9771-93504d639f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644361300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1644361300
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2790319201
Short name T47
Test name
Test status
Simulation time 8221452537 ps
CPU time 111.43 seconds
Started Feb 28 04:44:55 PM PST 24
Finished Feb 28 04:46:46 PM PST 24
Peak memory 199516 kb
Host smart-43811d65-ed7b-417b-a918-53d606f7337b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790319201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2790319201
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.123125148
Short name T322
Test name
Test status
Simulation time 44149722195 ps
CPU time 191.38 seconds
Started Feb 28 04:44:55 PM PST 24
Finished Feb 28 04:48:07 PM PST 24
Peak memory 199468 kb
Host smart-fb813d83-aa6e-4f2b-8dc2-7e5fa8c07843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123125148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.123125148
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2729417998
Short name T433
Test name
Test status
Simulation time 26002009438 ps
CPU time 78.26 seconds
Started Feb 28 04:44:51 PM PST 24
Finished Feb 28 04:46:10 PM PST 24
Peak memory 199476 kb
Host smart-89173606-66c5-40b3-b7e9-4b86c0fe85ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729417998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2729417998
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.93097628
Short name T264
Test name
Test status
Simulation time 382027246 ps
CPU time 4.62 seconds
Started Feb 28 04:44:51 PM PST 24
Finished Feb 28 04:44:56 PM PST 24
Peak memory 199460 kb
Host smart-043f5257-811b-47ae-a169-6bd366729499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93097628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.93097628
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2422076660
Short name T115
Test name
Test status
Simulation time 6013247694 ps
CPU time 311.37 seconds
Started Feb 28 04:44:54 PM PST 24
Finished Feb 28 04:50:05 PM PST 24
Peak memory 199564 kb
Host smart-c3b6b649-a4fc-4878-a8cb-516f34bc51ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422076660 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2422076660
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1432478184
Short name T170
Test name
Test status
Simulation time 101670488 ps
CPU time 0.94 seconds
Started Feb 28 04:44:55 PM PST 24
Finished Feb 28 04:44:56 PM PST 24
Peak memory 197320 kb
Host smart-406416f5-cebe-4a56-adde-e46b07351a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432478184 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1432478184
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1572739915
Short name T168
Test name
Test status
Simulation time 21995805458 ps
CPU time 379.03 seconds
Started Feb 28 04:45:02 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 199388 kb
Host smart-3c14135e-b542-4730-847d-d390fd598f41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572739915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.1572739915
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1785306709
Short name T223
Test name
Test status
Simulation time 6955324104 ps
CPU time 23.68 seconds
Started Feb 28 04:44:55 PM PST 24
Finished Feb 28 04:45:19 PM PST 24
Peak memory 199468 kb
Host smart-a2ec9da5-876a-486c-9c66-8c22559a22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785306709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1785306709
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3006500631
Short name T478
Test name
Test status
Simulation time 19613324 ps
CPU time 0.61 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:02 PM PST 24
Peak memory 193808 kb
Host smart-88f5b112-a465-4d4b-8be3-00ad6d4a038b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006500631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3006500631
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.526232969
Short name T514
Test name
Test status
Simulation time 594158739 ps
CPU time 18.86 seconds
Started Feb 28 04:44:58 PM PST 24
Finished Feb 28 04:45:18 PM PST 24
Peak memory 199416 kb
Host smart-df785543-80d9-4073-b0bc-acb10a2b4146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526232969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.526232969
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2835210695
Short name T173
Test name
Test status
Simulation time 5146844349 ps
CPU time 27.81 seconds
Started Feb 28 04:44:56 PM PST 24
Finished Feb 28 04:45:24 PM PST 24
Peak memory 199492 kb
Host smart-0beef898-64d7-420a-843a-e7e22ea9049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835210695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2835210695
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3772564035
Short name T431
Test name
Test status
Simulation time 1355112174 ps
CPU time 18.37 seconds
Started Feb 28 04:45:00 PM PST 24
Finished Feb 28 04:45:19 PM PST 24
Peak memory 199424 kb
Host smart-255ae57d-92b3-4c73-a2f6-7356c0b0be92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772564035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3772564035
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1474320262
Short name T268
Test name
Test status
Simulation time 480946824 ps
CPU time 25.45 seconds
Started Feb 28 04:44:57 PM PST 24
Finished Feb 28 04:45:23 PM PST 24
Peak memory 199460 kb
Host smart-0ac20422-881e-403c-8f42-681ffdb3cfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474320262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1474320262
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2690780753
Short name T366
Test name
Test status
Simulation time 3241386265 ps
CPU time 62.66 seconds
Started Feb 28 04:44:53 PM PST 24
Finished Feb 28 04:45:56 PM PST 24
Peak memory 199536 kb
Host smart-2d652d1f-6aa2-48ca-926e-0e59f81213e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690780753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2690780753
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3747148049
Short name T320
Test name
Test status
Simulation time 1172784895 ps
CPU time 1.41 seconds
Started Feb 28 04:44:53 PM PST 24
Finished Feb 28 04:44:55 PM PST 24
Peak memory 199228 kb
Host smart-02e7aafd-e886-4a49-b8a8-91ea1937de1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747148049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3747148049
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4058012967
Short name T260
Test name
Test status
Simulation time 71804710 ps
CPU time 1.26 seconds
Started Feb 28 04:45:00 PM PST 24
Finished Feb 28 04:45:01 PM PST 24
Peak memory 198816 kb
Host smart-af1cddac-9783-483d-9429-41237e4c6119
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058012967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4058012967
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.1813202573
Short name T491
Test name
Test status
Simulation time 20533683792 ps
CPU time 774.49 seconds
Started Feb 28 04:44:56 PM PST 24
Finished Feb 28 04:57:51 PM PST 24
Peak memory 215984 kb
Host smart-d9706c38-ddb5-4966-ac1b-4e95f24bffb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813202573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.1813202573
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1711120806
Short name T336
Test name
Test status
Simulation time 122553357 ps
CPU time 1.2 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:03 PM PST 24
Peak memory 198304 kb
Host smart-2d1a0650-a607-47ae-a462-c3b7d932bf6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711120806 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1711120806
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1452094432
Short name T326
Test name
Test status
Simulation time 22265589295 ps
CPU time 385.22 seconds
Started Feb 28 04:44:58 PM PST 24
Finished Feb 28 04:51:23 PM PST 24
Peak memory 199476 kb
Host smart-d5a7745d-42b9-4dc2-a353-4b493dfda510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452094432 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.1452094432
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2866457752
Short name T436
Test name
Test status
Simulation time 481116482 ps
CPU time 14.1 seconds
Started Feb 28 04:44:57 PM PST 24
Finished Feb 28 04:45:11 PM PST 24
Peak memory 199372 kb
Host smart-ab8ad07c-7193-482c-af02-dd1ccb92e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866457752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2866457752
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1279122464
Short name T517
Test name
Test status
Simulation time 12629547 ps
CPU time 0.6 seconds
Started Feb 28 04:45:05 PM PST 24
Finished Feb 28 04:45:06 PM PST 24
Peak memory 193872 kb
Host smart-7a515faf-ba78-4786-a4f8-c75f5ed02d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279122464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1279122464
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2287119249
Short name T432
Test name
Test status
Simulation time 7650636968 ps
CPU time 15.37 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:17 PM PST 24
Peak memory 215336 kb
Host smart-3233fd67-084e-466d-84fe-97b17cf49e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287119249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2287119249
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3457741929
Short name T328
Test name
Test status
Simulation time 10108985016 ps
CPU time 47.49 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:48 PM PST 24
Peak memory 199532 kb
Host smart-6d94653c-f7e8-4b95-9917-05838e66b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457741929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3457741929
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2769911494
Short name T165
Test name
Test status
Simulation time 60391187 ps
CPU time 0.74 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:02 PM PST 24
Peak memory 195400 kb
Host smart-14b342d3-23b3-483c-afe7-f6cb88206e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769911494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2769911494
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.351831835
Short name T174
Test name
Test status
Simulation time 8864351598 ps
CPU time 140.37 seconds
Started Feb 28 04:44:59 PM PST 24
Finished Feb 28 04:47:20 PM PST 24
Peak memory 199384 kb
Host smart-38ad1293-614e-4f15-a8d7-5ae370ebfa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351831835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.351831835
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.140924531
Short name T178
Test name
Test status
Simulation time 4000939300 ps
CPU time 53.99 seconds
Started Feb 28 04:45:01 PM PST 24
Finished Feb 28 04:45:55 PM PST 24
Peak memory 199436 kb
Host smart-927ad65f-9762-4b44-81bb-f8b11c2b5967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140924531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.140924531
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1996207052
Short name T179
Test name
Test status
Simulation time 215555128 ps
CPU time 1.82 seconds
Started Feb 28 04:45:02 PM PST 24
Finished Feb 28 04:45:04 PM PST 24
Peak memory 199416 kb
Host smart-8d6f253a-b2bc-4915-9781-ba0d3545a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996207052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1996207052
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1769477914
Short name T113
Test name
Test status
Simulation time 23152847703 ps
CPU time 563.72 seconds
Started Feb 28 04:44:59 PM PST 24
Finished Feb 28 04:54:23 PM PST 24
Peak memory 207932 kb
Host smart-23d426bb-d472-4b80-9c26-9a8bb9b6c77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769477914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1769477914
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1921689527
Short name T203
Test name
Test status
Simulation time 120154438 ps
CPU time 1.18 seconds
Started Feb 28 04:45:04 PM PST 24
Finished Feb 28 04:45:05 PM PST 24
Peak memory 198580 kb
Host smart-e5811d28-3ba5-497f-8105-c9c8e9e97eae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921689527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1921689527
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.726645015
Short name T198
Test name
Test status
Simulation time 10878540794 ps
CPU time 442.46 seconds
Started Feb 28 04:45:06 PM PST 24
Finished Feb 28 04:52:29 PM PST 24
Peak memory 199448 kb
Host smart-1e0173cb-4c64-4069-bb73-7912767f38f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726645015 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.hmac_test_sha_vectors.726645015
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.986089599
Short name T498
Test name
Test status
Simulation time 809323886 ps
CPU time 30.56 seconds
Started Feb 28 04:45:00 PM PST 24
Finished Feb 28 04:45:31 PM PST 24
Peak memory 199468 kb
Host smart-96605102-334b-4eca-a48c-4717a003b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986089599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.986089599
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1072707246
Short name T285
Test name
Test status
Simulation time 32704010 ps
CPU time 0.57 seconds
Started Feb 28 04:45:04 PM PST 24
Finished Feb 28 04:45:05 PM PST 24
Peak memory 193848 kb
Host smart-aee6c6f5-31b7-44f1-ad24-db24f1a4518e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072707246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1072707246
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.281762720
Short name T578
Test name
Test status
Simulation time 3348980981 ps
CPU time 42.62 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:46:04 PM PST 24
Peak memory 216856 kb
Host smart-fd16b2a1-fede-4581-a6ea-02f2a44e4d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281762720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.281762720
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2735629686
Short name T440
Test name
Test status
Simulation time 854115056 ps
CPU time 34.51 seconds
Started Feb 28 04:45:05 PM PST 24
Finished Feb 28 04:45:40 PM PST 24
Peak memory 199440 kb
Host smart-52a39ddb-d455-44b1-8b2c-dfa6843ebb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735629686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2735629686
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_error.592717821
Short name T221
Test name
Test status
Simulation time 48286701831 ps
CPU time 130.52 seconds
Started Feb 28 04:45:07 PM PST 24
Finished Feb 28 04:47:18 PM PST 24
Peak memory 199568 kb
Host smart-9e6c34e0-72db-4444-b6d7-75a2371dce01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592717821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.592717821
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2083274272
Short name T589
Test name
Test status
Simulation time 4323561444 ps
CPU time 16.78 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:45:38 PM PST 24
Peak memory 199420 kb
Host smart-19d5aa6c-3091-444f-9212-2fe968d76882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083274272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2083274272
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.88152846
Short name T313
Test name
Test status
Simulation time 1802176869 ps
CPU time 4 seconds
Started Feb 28 04:45:05 PM PST 24
Finished Feb 28 04:45:10 PM PST 24
Peak memory 199384 kb
Host smart-ddaf1cc0-857c-489b-9dc8-6b88f2cf0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88152846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.88152846
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3714352879
Short name T76
Test name
Test status
Simulation time 17240696139 ps
CPU time 216.89 seconds
Started Feb 28 04:45:04 PM PST 24
Finished Feb 28 04:48:41 PM PST 24
Peak memory 199500 kb
Host smart-fba13150-4d01-44fd-b38a-3027292752e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714352879 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3714352879
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.384242906
Short name T357
Test name
Test status
Simulation time 88909248 ps
CPU time 0.94 seconds
Started Feb 28 04:45:02 PM PST 24
Finished Feb 28 04:45:04 PM PST 24
Peak memory 197444 kb
Host smart-72f6d640-2cee-486d-8bdb-d1bf6fad4b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384242906 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.384242906
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.159266892
Short name T189
Test name
Test status
Simulation time 8770626250 ps
CPU time 438.55 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:52:40 PM PST 24
Peak memory 199384 kb
Host smart-c0a095c3-c112-4d25-bce5-bef274b64f16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159266892 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.hmac_test_sha_vectors.159266892
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.175348968
Short name T200
Test name
Test status
Simulation time 15828899487 ps
CPU time 52.09 seconds
Started Feb 28 04:45:09 PM PST 24
Finished Feb 28 04:46:02 PM PST 24
Peak memory 199408 kb
Host smart-91fc4347-425c-4c2a-b74d-2442ad659436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175348968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.175348968
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2209827665
Short name T227
Test name
Test status
Simulation time 15420929 ps
CPU time 0.57 seconds
Started Feb 28 04:45:07 PM PST 24
Finished Feb 28 04:45:08 PM PST 24
Peak memory 193832 kb
Host smart-9d521a56-2c57-4b81-9b1a-96052d0a3bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209827665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2209827665
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2154804890
Short name T51
Test name
Test status
Simulation time 360411374 ps
CPU time 5.23 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:45:27 PM PST 24
Peak memory 207536 kb
Host smart-17b31ad7-0353-4902-ac2e-0d1278f604a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154804890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2154804890
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1729952804
Short name T272
Test name
Test status
Simulation time 7714022020 ps
CPU time 24.82 seconds
Started Feb 28 04:45:12 PM PST 24
Finished Feb 28 04:45:37 PM PST 24
Peak memory 199460 kb
Host smart-e267fa05-4c9b-4756-8cd5-190f996eddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729952804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1729952804
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.309434369
Short name T441
Test name
Test status
Simulation time 1841063653 ps
CPU time 88.31 seconds
Started Feb 28 04:45:06 PM PST 24
Finished Feb 28 04:46:35 PM PST 24
Peak memory 199404 kb
Host smart-1c8d637d-56c4-42d6-a182-1c35e1950435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309434369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.309434369
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3971176724
Short name T412
Test name
Test status
Simulation time 6136118773 ps
CPU time 16.15 seconds
Started Feb 28 04:45:11 PM PST 24
Finished Feb 28 04:45:28 PM PST 24
Peak memory 199300 kb
Host smart-7416b1fb-08ef-4946-8719-93341e585e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971176724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3971176724
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1578998897
Short name T553
Test name
Test status
Simulation time 4205755872 ps
CPU time 37.67 seconds
Started Feb 28 04:45:04 PM PST 24
Finished Feb 28 04:45:42 PM PST 24
Peak memory 199488 kb
Host smart-27ad89b7-e6d0-4b2e-af35-8dee309e750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578998897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1578998897
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.267453966
Short name T419
Test name
Test status
Simulation time 159667879 ps
CPU time 3.55 seconds
Started Feb 28 04:45:06 PM PST 24
Finished Feb 28 04:45:10 PM PST 24
Peak memory 199380 kb
Host smart-75a41e01-dd1f-4d0e-8f12-514b1c44e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267453966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.267453966
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3523097317
Short name T588
Test name
Test status
Simulation time 175343565 ps
CPU time 1.12 seconds
Started Feb 28 04:45:07 PM PST 24
Finished Feb 28 04:45:08 PM PST 24
Peak memory 198084 kb
Host smart-5c2d1d1a-6159-4e49-9507-b78528a92d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523097317 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3523097317
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1012628586
Short name T297
Test name
Test status
Simulation time 41030400561 ps
CPU time 467.48 seconds
Started Feb 28 04:45:11 PM PST 24
Finished Feb 28 04:52:59 PM PST 24
Peak memory 199372 kb
Host smart-7a147234-f24d-4130-8d6c-3e63ebfb6abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012628586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.1012628586
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3758373624
Short name T494
Test name
Test status
Simulation time 1486077531 ps
CPU time 14.18 seconds
Started Feb 28 04:45:10 PM PST 24
Finished Feb 28 04:45:25 PM PST 24
Peak memory 199464 kb
Host smart-03564baa-f7ec-4d05-8c89-5d9375e98396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758373624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3758373624
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2012404003
Short name T554
Test name
Test status
Simulation time 53535717 ps
CPU time 0.66 seconds
Started Feb 28 04:45:15 PM PST 24
Finished Feb 28 04:45:15 PM PST 24
Peak memory 194080 kb
Host smart-17ac448e-6b2c-4843-9436-8883536b03fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012404003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2012404003
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3151696157
Short name T444
Test name
Test status
Simulation time 6106458008 ps
CPU time 52.81 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:46:14 PM PST 24
Peak memory 230808 kb
Host smart-fdfa397a-263f-48e6-8ab2-9b0d470b5319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151696157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3151696157
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3884312710
Short name T65
Test name
Test status
Simulation time 1641894590 ps
CPU time 37.53 seconds
Started Feb 28 04:45:12 PM PST 24
Finished Feb 28 04:45:49 PM PST 24
Peak memory 199452 kb
Host smart-4ccf22ca-c69a-4510-94fe-4b02ece78c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884312710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3884312710
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3229563229
Short name T466
Test name
Test status
Simulation time 747099918 ps
CPU time 19.43 seconds
Started Feb 28 04:45:12 PM PST 24
Finished Feb 28 04:45:31 PM PST 24
Peak memory 199232 kb
Host smart-f46ea754-a212-48f4-9de2-5fca82d76fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229563229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3229563229
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1119420396
Short name T389
Test name
Test status
Simulation time 1891667278 ps
CPU time 92.39 seconds
Started Feb 28 04:45:10 PM PST 24
Finished Feb 28 04:46:43 PM PST 24
Peak memory 199456 kb
Host smart-b977bb40-1f5e-4fba-b046-42c1a01d31f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119420396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1119420396
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3014741787
Short name T399
Test name
Test status
Simulation time 108785702656 ps
CPU time 117.38 seconds
Started Feb 28 04:45:12 PM PST 24
Finished Feb 28 04:47:09 PM PST 24
Peak memory 199572 kb
Host smart-6fa5806d-cadb-4539-a255-7ff1fee9c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014741787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3014741787
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2971087784
Short name T237
Test name
Test status
Simulation time 361259846 ps
CPU time 2.42 seconds
Started Feb 28 04:45:21 PM PST 24
Finished Feb 28 04:45:24 PM PST 24
Peak memory 199148 kb
Host smart-9a9a395c-0a26-4d9b-90d7-6712b2e4379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971087784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2971087784
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.598878023
Short name T516
Test name
Test status
Simulation time 33050736053 ps
CPU time 964.08 seconds
Started Feb 28 04:45:10 PM PST 24
Finished Feb 28 05:01:14 PM PST 24
Peak memory 199572 kb
Host smart-ce08c4fd-5df8-428e-a024-6b1e3848440c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598878023 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.598878023
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1177653310
Short name T401
Test name
Test status
Simulation time 181712450 ps
CPU time 1.05 seconds
Started Feb 28 04:45:11 PM PST 24
Finished Feb 28 04:45:13 PM PST 24
Peak memory 197200 kb
Host smart-849504b2-28ac-4d21-b18e-d59739bed66b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177653310 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1177653310
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1807969494
Short name T167
Test name
Test status
Simulation time 110073003150 ps
CPU time 473.01 seconds
Started Feb 28 04:45:12 PM PST 24
Finished Feb 28 04:53:06 PM PST 24
Peak memory 199460 kb
Host smart-4bcbf34f-90de-4eae-a604-ab12f623a6c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807969494 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.1807969494
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1935834028
Short name T305
Test name
Test status
Simulation time 3716418058 ps
CPU time 14.54 seconds
Started Feb 28 04:45:13 PM PST 24
Finished Feb 28 04:45:28 PM PST 24
Peak memory 199304 kb
Host smart-f5586eee-3800-459d-862e-2541496f7ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935834028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1935834028
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.18344841
Short name T286
Test name
Test status
Simulation time 17486670 ps
CPU time 0.62 seconds
Started Feb 28 04:42:58 PM PST 24
Finished Feb 28 04:42:59 PM PST 24
Peak memory 194056 kb
Host smart-719a5da2-a4fe-4903-9fd7-7cfe4609db05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.18344841
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3866849295
Short name T453
Test name
Test status
Simulation time 5280443668 ps
CPU time 45.84 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:43:39 PM PST 24
Peak memory 221044 kb
Host smart-6c98ec8f-d4b7-4f94-810e-8c5d91615be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866849295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3866849295
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3805042814
Short name T324
Test name
Test status
Simulation time 2623066412 ps
CPU time 71.57 seconds
Started Feb 28 04:42:58 PM PST 24
Finished Feb 28 04:44:10 PM PST 24
Peak memory 199460 kb
Host smart-13432faf-b43a-4f2a-9080-463d6062d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805042814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3805042814
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.603035073
Short name T98
Test name
Test status
Simulation time 5716053302 ps
CPU time 48.35 seconds
Started Feb 28 04:42:53 PM PST 24
Finished Feb 28 04:43:41 PM PST 24
Peak memory 199496 kb
Host smart-3f62aa31-0d79-4992-bf49-c13798303bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603035073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.603035073
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2813579605
Short name T128
Test name
Test status
Simulation time 44028201275 ps
CPU time 165.26 seconds
Started Feb 28 04:42:56 PM PST 24
Finished Feb 28 04:45:41 PM PST 24
Peak memory 199484 kb
Host smart-ed8192ac-06f2-44ea-a96b-868d1df8f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813579605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2813579605
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1835291171
Short name T226
Test name
Test status
Simulation time 931729530 ps
CPU time 49.04 seconds
Started Feb 28 04:42:54 PM PST 24
Finished Feb 28 04:43:43 PM PST 24
Peak memory 199508 kb
Host smart-dff8b6ea-02be-4b00-a673-bd5fecd63ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835291171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1835291171
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2586806949
Short name T409
Test name
Test status
Simulation time 798344019 ps
CPU time 3.74 seconds
Started Feb 28 04:42:51 PM PST 24
Finished Feb 28 04:42:55 PM PST 24
Peak memory 199408 kb
Host smart-556a54c6-3ef0-4f36-9098-1cacaf7ed9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586806949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2586806949
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2386634802
Short name T101
Test name
Test status
Simulation time 89022008079 ps
CPU time 1171.94 seconds
Started Feb 28 04:42:59 PM PST 24
Finished Feb 28 05:02:31 PM PST 24
Peak memory 199476 kb
Host smart-55097b55-de6f-4a95-b01a-a7d7faf1ad6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386634802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2386634802
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1121463663
Short name T581
Test name
Test status
Simulation time 468587978 ps
CPU time 0.9 seconds
Started Feb 28 04:42:55 PM PST 24
Finished Feb 28 04:42:57 PM PST 24
Peak memory 196944 kb
Host smart-6792b80c-e610-4289-b833-7a91232b2739
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121463663 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1121463663
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2194121096
Short name T240
Test name
Test status
Simulation time 32888321304 ps
CPU time 431.64 seconds
Started Feb 28 04:42:57 PM PST 24
Finished Feb 28 04:50:09 PM PST 24
Peak memory 199476 kb
Host smart-12946d24-3075-423d-8f5a-718c1ab75a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194121096 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2194121096
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1316656191
Short name T241
Test name
Test status
Simulation time 3118481484 ps
CPU time 55.25 seconds
Started Feb 28 04:42:55 PM PST 24
Finished Feb 28 04:43:50 PM PST 24
Peak memory 199524 kb
Host smart-780b612a-e621-4f30-ba36-cf317eafe8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316656191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1316656191
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3420036238
Short name T361
Test name
Test status
Simulation time 13809341 ps
CPU time 0.57 seconds
Started Feb 28 04:42:58 PM PST 24
Finished Feb 28 04:42:59 PM PST 24
Peak memory 193832 kb
Host smart-0fb6abd3-4a1f-4302-a43e-63bdc2bab382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420036238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3420036238
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1852411607
Short name T9
Test name
Test status
Simulation time 4436484555 ps
CPU time 33.43 seconds
Started Feb 28 04:43:00 PM PST 24
Finished Feb 28 04:43:34 PM PST 24
Peak memory 215436 kb
Host smart-7450ed77-37ca-4c26-8e2a-25544e71a799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852411607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1852411607
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1212336796
Short name T350
Test name
Test status
Simulation time 6104900010 ps
CPU time 28.62 seconds
Started Feb 28 04:42:59 PM PST 24
Finished Feb 28 04:43:28 PM PST 24
Peak memory 199548 kb
Host smart-767fc54c-5609-4ba7-8a8b-1136fd0a99b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212336796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1212336796
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3410700437
Short name T527
Test name
Test status
Simulation time 201566134 ps
CPU time 6.29 seconds
Started Feb 28 04:43:01 PM PST 24
Finished Feb 28 04:43:07 PM PST 24
Peak memory 199480 kb
Host smart-426fcf4c-a538-4dc1-bfdd-0930cc046442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410700437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3410700437
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3117493929
Short name T509
Test name
Test status
Simulation time 10867943469 ps
CPU time 95.65 seconds
Started Feb 28 04:43:00 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 199444 kb
Host smart-1781c846-aaa8-4e2d-baa5-d9386649539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117493929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3117493929
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3348056344
Short name T427
Test name
Test status
Simulation time 699595751 ps
CPU time 35.41 seconds
Started Feb 28 04:42:59 PM PST 24
Finished Feb 28 04:43:34 PM PST 24
Peak memory 199468 kb
Host smart-3e01e63f-4bfa-4c6f-8139-df383296f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348056344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3348056344
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.657148183
Short name T161
Test name
Test status
Simulation time 240617539 ps
CPU time 2.65 seconds
Started Feb 28 04:42:57 PM PST 24
Finished Feb 28 04:43:00 PM PST 24
Peak memory 199444 kb
Host smart-6d00e340-6a1a-4e15-885a-0016adcb55ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657148183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.657148183
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1529534831
Short name T118
Test name
Test status
Simulation time 44338143627 ps
CPU time 1131.12 seconds
Started Feb 28 04:43:02 PM PST 24
Finished Feb 28 05:01:54 PM PST 24
Peak memory 199476 kb
Host smart-e3f991b8-6490-436a-9fe1-74768b92ee9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529534831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1529534831
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2598909315
Short name T556
Test name
Test status
Simulation time 62008117 ps
CPU time 1.08 seconds
Started Feb 28 04:42:59 PM PST 24
Finished Feb 28 04:43:00 PM PST 24
Peak memory 198456 kb
Host smart-2fba9f5e-0809-4acf-8a19-70cf4a2a8127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598909315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2598909315
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3335500186
Short name T163
Test name
Test status
Simulation time 26969116473 ps
CPU time 429.31 seconds
Started Feb 28 04:42:58 PM PST 24
Finished Feb 28 04:50:07 PM PST 24
Peak memory 199408 kb
Host smart-83831a58-b84f-4309-9cb9-b8f118903ce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335500186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3335500186
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2723644080
Short name T176
Test name
Test status
Simulation time 2610025969 ps
CPU time 41.66 seconds
Started Feb 28 04:43:03 PM PST 24
Finished Feb 28 04:43:45 PM PST 24
Peak memory 199320 kb
Host smart-719486e7-18f1-4b47-be89-530d80e81315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723644080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2723644080
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3751940060
Short name T230
Test name
Test status
Simulation time 46874249 ps
CPU time 0.62 seconds
Started Feb 28 04:43:05 PM PST 24
Finished Feb 28 04:43:07 PM PST 24
Peak memory 195112 kb
Host smart-5efb9875-1043-47b4-ac9e-54f4a3d30854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751940060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3751940060
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1127577375
Short name T245
Test name
Test status
Simulation time 2649773866 ps
CPU time 43.3 seconds
Started Feb 28 04:43:00 PM PST 24
Finished Feb 28 04:43:44 PM PST 24
Peak memory 216752 kb
Host smart-9c463eaa-3e01-497e-a544-99eea60a53fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127577375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1127577375
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3028403170
Short name T108
Test name
Test status
Simulation time 3321223722 ps
CPU time 8.94 seconds
Started Feb 28 04:43:01 PM PST 24
Finished Feb 28 04:43:10 PM PST 24
Peak memory 199472 kb
Host smart-a2b621dd-8182-4924-970b-e65a3d42d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028403170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3028403170
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1047223088
Short name T188
Test name
Test status
Simulation time 14456487112 ps
CPU time 119.84 seconds
Started Feb 28 04:43:02 PM PST 24
Finished Feb 28 04:45:03 PM PST 24
Peak memory 199456 kb
Host smart-df202116-d38d-4803-ab2d-03271c0f518d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047223088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1047223088
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1605423634
Short name T456
Test name
Test status
Simulation time 1521033708 ps
CPU time 77.5 seconds
Started Feb 28 04:43:04 PM PST 24
Finished Feb 28 04:44:22 PM PST 24
Peak memory 199356 kb
Host smart-59ee30b7-7859-41ff-bba9-95fa6d58f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605423634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1605423634
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2241294952
Short name T325
Test name
Test status
Simulation time 9238551376 ps
CPU time 89.88 seconds
Started Feb 28 04:43:01 PM PST 24
Finished Feb 28 04:44:31 PM PST 24
Peak memory 199584 kb
Host smart-2e971ea2-c901-4263-a806-ac49a5037527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241294952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2241294952
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3641516206
Short name T565
Test name
Test status
Simulation time 287900990 ps
CPU time 3.89 seconds
Started Feb 28 04:43:00 PM PST 24
Finished Feb 28 04:43:04 PM PST 24
Peak memory 199400 kb
Host smart-f8043a20-636c-41e0-ac23-07faf5813b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641516206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3641516206
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.185576566
Short name T73
Test name
Test status
Simulation time 23164242299 ps
CPU time 114.29 seconds
Started Feb 28 04:43:06 PM PST 24
Finished Feb 28 04:45:01 PM PST 24
Peak memory 225648 kb
Host smart-fd301575-343c-4746-8880-9a185cd4b59d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185576566 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.185576566
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2871827896
Short name T593
Test name
Test status
Simulation time 31355333 ps
CPU time 1.29 seconds
Started Feb 28 04:43:01 PM PST 24
Finished Feb 28 04:43:02 PM PST 24
Peak memory 198488 kb
Host smart-031dd3e9-ef3d-4501-9d65-02dc7f0ca472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871827896 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2871827896
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.191153249
Short name T601
Test name
Test status
Simulation time 16135363862 ps
CPU time 384.76 seconds
Started Feb 28 04:43:08 PM PST 24
Finished Feb 28 04:49:34 PM PST 24
Peak memory 199300 kb
Host smart-1806a4cd-2039-447c-b6e7-d0489cd28b0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191153249 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.191153249
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1569347923
Short name T333
Test name
Test status
Simulation time 1475219196 ps
CPU time 22.1 seconds
Started Feb 28 04:43:03 PM PST 24
Finished Feb 28 04:43:25 PM PST 24
Peak memory 199420 kb
Host smart-1fadb2fa-0bd6-4acb-b866-8181bf7af166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569347923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1569347923
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1655954085
Short name T15
Test name
Test status
Simulation time 27923238 ps
CPU time 0.61 seconds
Started Feb 28 04:43:07 PM PST 24
Finished Feb 28 04:43:08 PM PST 24
Peak memory 193992 kb
Host smart-2def4f78-1424-4841-8891-5b4aa1701bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655954085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1655954085
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1952721887
Short name T577
Test name
Test status
Simulation time 4250221754 ps
CPU time 23.87 seconds
Started Feb 28 04:43:10 PM PST 24
Finished Feb 28 04:43:34 PM PST 24
Peak memory 222832 kb
Host smart-ce9ea805-aea6-4faf-b791-c23a0889994e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952721887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1952721887
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2461658769
Short name T458
Test name
Test status
Simulation time 5115877981 ps
CPU time 37.59 seconds
Started Feb 28 04:43:13 PM PST 24
Finished Feb 28 04:43:51 PM PST 24
Peak memory 199568 kb
Host smart-4a1a3010-072b-4ed9-8d45-d592a63f73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461658769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2461658769
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3891848928
Short name T546
Test name
Test status
Simulation time 149421510 ps
CPU time 8.1 seconds
Started Feb 28 04:43:02 PM PST 24
Finished Feb 28 04:43:10 PM PST 24
Peak memory 199420 kb
Host smart-8bddf001-67df-49be-998b-75ed42ffabe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891848928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3891848928
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.19188704
Short name T526
Test name
Test status
Simulation time 16623396933 ps
CPU time 69.33 seconds
Started Feb 28 04:43:09 PM PST 24
Finished Feb 28 04:44:18 PM PST 24
Peak memory 199512 kb
Host smart-e6d0d004-54f4-42e9-a8c6-d98e244ccc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19188704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.19188704
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3485193293
Short name T402
Test name
Test status
Simulation time 2711097514 ps
CPU time 35.56 seconds
Started Feb 28 04:43:02 PM PST 24
Finished Feb 28 04:43:37 PM PST 24
Peak memory 199540 kb
Host smart-d5c54c88-72f1-48a4-ae6d-5940d1c778b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485193293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3485193293
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2842258119
Short name T11
Test name
Test status
Simulation time 643890444 ps
CPU time 3.33 seconds
Started Feb 28 04:43:08 PM PST 24
Finished Feb 28 04:43:12 PM PST 24
Peak memory 199276 kb
Host smart-7ce8e86d-bbd4-448e-a21b-cfc33688b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842258119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2842258119
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2068559113
Short name T120
Test name
Test status
Simulation time 741050072848 ps
CPU time 1109.22 seconds
Started Feb 28 04:43:07 PM PST 24
Finished Feb 28 05:01:37 PM PST 24
Peak memory 199580 kb
Host smart-b474daac-cb7b-4962-a988-65c0662fda4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068559113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2068559113
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3913285077
Short name T561
Test name
Test status
Simulation time 119030440 ps
CPU time 1.27 seconds
Started Feb 28 04:43:06 PM PST 24
Finished Feb 28 04:43:08 PM PST 24
Peak memory 199344 kb
Host smart-ef7bdc65-a59d-4b4f-8692-17c525be302b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913285077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3913285077
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.491472174
Short name T280
Test name
Test status
Simulation time 109724236778 ps
CPU time 449.97 seconds
Started Feb 28 04:43:05 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 199352 kb
Host smart-7347be9a-b66c-43b8-8684-79f4958a7046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491472174 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_sha_vectors.491472174
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1201907119
Short name T152
Test name
Test status
Simulation time 1734331226 ps
CPU time 53.88 seconds
Started Feb 28 04:43:04 PM PST 24
Finished Feb 28 04:43:59 PM PST 24
Peak memory 199492 kb
Host smart-c081110d-984e-48ca-93d5-3bb799d4d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201907119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1201907119
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3318475914
Short name T41
Test name
Test status
Simulation time 19965391428 ps
CPU time 1022.8 seconds
Started Feb 28 04:45:18 PM PST 24
Finished Feb 28 05:02:21 PM PST 24
Peak memory 207840 kb
Host smart-66ced0db-f754-4a39-a9a4-9d7c2e540ef0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318475914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.3318475914
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1062463645
Short name T33
Test name
Test status
Simulation time 40271689 ps
CPU time 0.57 seconds
Started Feb 28 04:43:17 PM PST 24
Finished Feb 28 04:43:18 PM PST 24
Peak memory 194072 kb
Host smart-eea31d48-d990-4ef0-ab9e-165e17996af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062463645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1062463645
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2633733634
Short name T17
Test name
Test status
Simulation time 1039406723 ps
CPU time 19.5 seconds
Started Feb 28 04:43:04 PM PST 24
Finished Feb 28 04:43:24 PM PST 24
Peak memory 199504 kb
Host smart-286393b0-fcd6-447b-afdb-0f6e56d8b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633733634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2633733634
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2428057609
Short name T224
Test name
Test status
Simulation time 2168602497 ps
CPU time 118.1 seconds
Started Feb 28 04:43:05 PM PST 24
Finished Feb 28 04:45:04 PM PST 24
Peak memory 199496 kb
Host smart-91c3d354-e613-4549-bee5-ebc33bcf3196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428057609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2428057609
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2887222361
Short name T533
Test name
Test status
Simulation time 616686218 ps
CPU time 7.24 seconds
Started Feb 28 04:43:12 PM PST 24
Finished Feb 28 04:43:20 PM PST 24
Peak memory 199360 kb
Host smart-f83213d3-19e8-4c56-bd7a-fedbc257125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887222361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2887222361
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.381957055
Short name T591
Test name
Test status
Simulation time 3395147643 ps
CPU time 12.6 seconds
Started Feb 28 04:43:07 PM PST 24
Finished Feb 28 04:43:20 PM PST 24
Peak memory 199520 kb
Host smart-4ad96560-7cd8-41cd-8e6c-5833b11db5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381957055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.381957055
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4256286438
Short name T488
Test name
Test status
Simulation time 812114457 ps
CPU time 2.47 seconds
Started Feb 28 04:43:04 PM PST 24
Finished Feb 28 04:43:08 PM PST 24
Peak memory 199400 kb
Host smart-06b12245-dd67-4131-aefe-0327d62cfae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256286438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4256286438
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.659934984
Short name T229
Test name
Test status
Simulation time 51908670380 ps
CPU time 433.38 seconds
Started Feb 28 04:43:10 PM PST 24
Finished Feb 28 04:50:24 PM PST 24
Peak memory 199536 kb
Host smart-7a146085-fbd8-4a59-8148-80d70847d7fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659934984 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.659934984
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2407591381
Short name T518
Test name
Test status
Simulation time 30760297 ps
CPU time 1.15 seconds
Started Feb 28 04:43:09 PM PST 24
Finished Feb 28 04:43:11 PM PST 24
Peak memory 198652 kb
Host smart-fffc4305-15b3-439b-ba35-93ee931b609e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407591381 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2407591381
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3637297435
Short name T3
Test name
Test status
Simulation time 100034370751 ps
CPU time 407.69 seconds
Started Feb 28 04:43:09 PM PST 24
Finished Feb 28 04:49:57 PM PST 24
Peak memory 199428 kb
Host smart-781fd713-5532-4881-8418-48fa80ccb4e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637297435 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.3637297435
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2689613516
Short name T510
Test name
Test status
Simulation time 2386720877 ps
CPU time 83.62 seconds
Started Feb 28 04:43:11 PM PST 24
Finished Feb 28 04:44:35 PM PST 24
Peak memory 199456 kb
Host smart-3fd246c6-542b-42d7-8abf-ad70b761be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689613516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2689613516
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.3931594351
Short name T60
Test name
Test status
Simulation time 4768586185 ps
CPU time 61.28 seconds
Started Feb 28 04:45:23 PM PST 24
Finished Feb 28 04:46:24 PM PST 24
Peak memory 199544 kb
Host smart-42a1a41f-5c92-4d19-ac12-72e44721d8bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931594351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.3931594351
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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