Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42485635

1

T1

8

T2

469294

T3

38042

full_word

39770146

1

T1

2

T2

494293

T3

31415

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82255441	1			T1	10		T2	963587		T3	69457
auto[TlIntgErrCmd]	106	1			T47	10		T48	7		T49	3
auto[TlIntgErrData]	119	1			T47	3		T48	6		T49	3
auto[TlIntgErrBoth]	115	1			T47	7		T48	7		T49	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32776471

1

T1

1

T2

387632

T3

28104

auto[1]

49479310

1

T1

9

T2

575955

T3

41353

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17497811	1			T1	1		T2	193985		T3	14078
auto[TlIntgErrNone]	partial	auto[1]	24987519	1			T1	7		T2	275309		T3	23964
auto[TlIntgErrNone]	full_word	auto[0]	15278494	1			T2	193647		T3	14026		T4	139869
auto[TlIntgErrNone]	full_word	auto[1]	24491617	1			T1	2		T2	300646		T3	17389
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T47	4		T48	5		T49	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T47	5		T48	2		T49	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T47	1		T119	2		T121	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T47	1		T48	3		T49	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T47	2		T48	3		T49	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T123	1		T121	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T114	1		T121	2		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T47	2		T48	4		T49	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T47	4		T48	3		T49	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T47	1		T118	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T113	1		T118	1		T125	1