Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.10	100.00	96.42			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.10	100.00	96.42			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.10	100.00	96.42			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.48	99.83	97.56	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_continue	100.00	100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_cmd_hash_stop	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_2	100.00	100.00
u_key_3	100.00	100.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_msg_length_lower	100.00	100.00
u_msg_length_upper	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		245	245	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	763	1	1	100.00
CONT_ASSIGN	770	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
CONT_ASSIGN	826	1	1	100.00
CONT_ASSIGN	833	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	889	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	938	1	1	100.00
CONT_ASSIGN	952	1	1	100.00
CONT_ASSIGN	959	1	1	100.00
CONT_ASSIGN	973	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1001	1	1	100.00
CONT_ASSIGN	1015	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1036	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1064	1	1	100.00
CONT_ASSIGN	1078	1	1	100.00
CONT_ASSIGN	1084	1	1	100.00
CONT_ASSIGN	1098	1	1	100.00
CONT_ASSIGN	1104	1	1	100.00
CONT_ASSIGN	1118	1	1	100.00
ALWAYS	1124	28	28	100.00
CONT_ASSIGN	1154	1	1	100.00
ALWAYS	1158	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1191	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1195	1	1	100.00
CONT_ASSIGN	1196	1	1	100.00
CONT_ASSIGN	1198	1	1	100.00
CONT_ASSIGN	1200	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1203	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1209	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1212	1	1	100.00
CONT_ASSIGN	1213	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1216	1	1	100.00
CONT_ASSIGN	1218	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1222	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1296	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
ALWAYS	1303	28	28	100.00
ALWAYS	1335	43	43	100.00
CONT_ASSIGN	1470	0	0
CONT_ASSIGN	1478	1	1	100.00
CONT_ASSIGN	1479	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
442	1	1
457	1	1
473	1	1
489	1	1
495	1	1
509	1	1
515	1	1
530	1	1
546	1	1
562	1	1
578	1	1
584	1	1
599	1	1
615	1	1
631	1	1
647	1	1
728	1	1
742	1	1
749	1	1
763	1	1
770	1	1
784	1	1
791	1	1
805	1	1
812	1	1
826	1	1
833	1	1
847	1	1
854	1	1
868	1	1
875	1	1
889	1	1
896	1	1
910	1	1
917	1	1
931	1	1
938	1	1
952	1	1
959	1	1
973	1	1
980	1	1
994	1	1
1001	1	1
1015	1	1
1022	1	1
1036	1	1
1043	1	1
1057	1	1
1064	1	1
1078	1	1
1084	1	1
1098	1	1
1104	1	1
1118	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1154	1	1
1158	1	1
1189	1	1
1191	1	1
1193	1	1
1195	1	1
1196	1	1
1198	1	1
1200	1	1
1202	1	1
1203	1	1
1205	1	1
1207	1	1
1209	1	1
1210	1	1
1212	1	1
1213	1	1
1214	1	1
1216	1	1
1218	1	1
1220	1	1
1222	1	1
1223	1	1
1225	1	1
1227	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1235	1	1
1236	1	1
1238	1	1
1239	1	1
1241	1	1
1242	1	1
1244	1	1
1245	1	1
1247	1	1
1248	1	1
1250	1	1
1251	1	1
1253	1	1
1254	1	1
1256	1	1
1257	1	1
1259	1	1
1260	1	1
1261	1	1
1263	1	1
1264	1	1
1265	1	1
1267	1	1
1268	1	1
1269	1	1
1271	1	1
1272	1	1
1273	1	1
1275	1	1
1276	1	1
1277	1	1
1279	1	1
1280	1	1
1281	1	1
1283	1	1
1284	1	1
1285	1	1
1287	1	1
1288	1	1
1289	1	1
1291	1	1
1292	1	1
1293	1	1
1295	1	1
1296	1	1
1297	1	1
1299	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1335	1	1
1336	1	1
1338	1	1
1339	1	1
1340	1	1
1344	1	1
1345	1	1
1346	1	1
1350	1	1
1351	1	1
1352	1	1
1356	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1367	1	1
1368	1	1
1369	1	1
1370	1	1
1374	1	1
1375	1	1
1376	1	1
1380	1	1
1384	1	1
1388	1	1
1392	1	1
1396	1	1
1400	1	1
1404	1	1
1408	1	1
1412	1	1
1416	1	1
1420	1	1
1424	1	1
1428	1	1
1432	1	1
1436	1	1
1440	1	1
1444	1	1
1448	1	1
1452	1	1
1456	1	1
1470		unreachable
1478	1	1
1479	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	335	323	96.42
Logical	335	323	96.42
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T12
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T47,T48,T49

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T18,T19,T20
0	1	0	Covered	T47,T48,T49
1	0	0	Covered	T18,T19,T20

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T47,T48,T49
0	1	0	Covered	T5,T11,T12
1	0	0	Covered	T5,T11,T12

 LINE       1125
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1126
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1127
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1128
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1129
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CFG_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1130
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1131
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1132
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1133
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1134
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1135
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1136
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1137
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1138
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1139
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_5_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1140
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_6_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1141
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_7_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1142
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1143
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1144
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1145
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1146
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1147
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1148
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1149
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1150
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1151
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1154
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1154
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1158
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T11,T12

 LINE       1158
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
27 (addr_hit[26] & ((|(4'...	Covered	T2,T3,T4
26 (addr_hit[25] & ((|(4'...	Covered	T2,T3,T4
25 (addr_hit[24] & ((|(4'...	Covered	T2,T3,T4
24 (addr_hit[23] & ((|(4'...	Covered	T2,T3,T4
23 (addr_hit[22] & ((|(4'...	Covered	T2,T3,T4
22 (addr_hit[21] & ((|(4'...	Covered	T2,T3,T4
21 (addr_hit[20] & ((|(4'...	Covered	T2,T3,T4
20 (addr_hit[19] & ((|(4'...	Covered	T2,T3,T4
19 (addr_hit[18] & ((|(4'...	Covered	T2,T3,T4
18 (addr_hit[17] & ((|(4'...	Covered	T2,T3,T4
17 (addr_hit[16] & ((|(4'...	Covered	T2,T3,T5
16 (addr_hit[15] & ((|(4'...	Covered	T2,T3,T5
15 (addr_hit[14] & ((|(4'...	Covered	T2,T3,T5
14 (addr_hit[13] & ((|(4'...	Covered	T2,T3,T5
13 (addr_hit[12] & ((|(4'...	Covered	T2,T3,T5
12 (addr_hit[11] & ((|(4'...	Covered	T2,T3,T5
11 (addr_hit[10] & ((|(4'...	Covered	T2,T3,T5
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T3,T5
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T3,T5
8 (addr_hit[7] & ((|(4'b...	Covered	T2,T3,T4
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T3,T4
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T3,T5
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T3,T5
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T3,T5
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T3,T5
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T3,T5
1 (addr_hit[0] & ((|(4'b...	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1158
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1158
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1189
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1196
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1203
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T5,T50

 LINE       1210
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T1,T9,T10

 LINE       1213
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T5,T11,T12

 LINE       1214
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1223
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1232
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1233
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T5,T13,T14

 LINE       1236
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1239
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1242
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1245
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1248
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1251
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1254
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1257
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T2,T3,T4

 LINE       1260
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1261
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1264
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1265
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1268
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1269
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1272
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1273
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1276
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1277
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1280
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1281
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1284
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1285
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1288
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1289
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1292
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1293
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

 LINE       1296
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1297
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T5,T11,T12
1	1	1	Covered	T51,T52,T53

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		37	37	100.00
TERNARY	1154	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1336	28	28	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1154	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T47,T48,T49
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1336	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	464475987	56326501	0	0
reAfterRv	464475987	56326501	0	0
rePulse	464475987	31030915	0	0
wePulse	464475987	25295586	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	56326501	0	0
T1	1194	10	0	0
T2	879623	765506	0	0
T3	146081	42116	0	0
T4	747203	559635	0	0
T5	260399	610491	0	0
T6	104173	122074	0	0
T9	1095	20	0	0
T15	13326	2026	0	0
T16	476347	377397	0	0
T17	145181	6052	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	56326501	0	0
T1	1194	10	0	0
T2	879623	765506	0	0
T3	146081	42116	0	0
T4	747203	559635	0	0
T5	260399	610491	0	0
T6	104173	122074	0	0
T9	1095	20	0	0
T15	13326	2026	0	0
T16	476347	377397	0	0
T17	145181	6052	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	31030915	0	0
T1	1194	1	0	0
T2	879623	387632	0	0
T3	146081	28104	0	0
T4	747203	279789	0	0
T5	260399	399743	0	0
T6	104173	63343	0	0
T9	1095	1	0	0
T15	13326	1376	0	0
T16	476347	191037	0	0
T17	145181	5569	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	25295586	0	0
T1	1194	9	0	0
T2	879623	377874	0	0
T3	146081	14012	0	0
T4	747203	279846	0	0
T5	260399	210748	0	0
T6	104173	58731	0	0
T9	1095	19	0	0
T15	13326	650	0	0
T16	476347	186360	0	0
T17	145181	483	0	0