Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	464475987	2185349	0	0
intr_enable_rd_A	464475987	3944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	2185349	0	0
T5	260399	119620	0	0
T6	104173	0	0	0
T7	859344	0	0	0
T8	158921	0	0	0
T9	1095	0	0	0
T11	0	96954	0	0
T12	0	45101	0	0
T15	13326	0	0	0
T16	476347	0	0	0
T17	145181	0	0	0
T31	188557	0	0	0
T32	419819	0	0	0
T33	0	59040	0	0
T34	0	183713	0	0
T35	0	91094	0	0
T36	0	159148	0	0
T52	0	10	0	0
T54	0	384838	0	0
T55	0	78024	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464475987	3944	0	0
T2	879623	35	0	0
T3	146081	0	0	0
T4	747203	0	0	0
T5	260399	0	0	0
T6	104173	0	0	0
T7	859344	0	0	0
T9	1095	0	0	0
T15	13326	0	0	0
T16	476347	0	0	0
T17	145181	0	0	0
T50	0	139	0	0
T56	0	16	0	0
T57	0	41	0	0
T58	0	9	0	0
T59	0	48	0	0
T60	0	31	0	0
T61	0	25	0	0
T62	0	17	0	0
T63	0	125	0	0