Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.77	97.17	88.24		100.00	89.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	96.79	97.17	95.45		100.00	94.55

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	97.17	95.45		100.00	94.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	97.17	95.45		100.00	94.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		106	103	97.17
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	145	8	7	87.50
ALWAYS	160	6	6	100.00
ALWAYS	170	4	4	100.00
ALWAYS	178	6	6	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	3	3	100.00
ALWAYS	195	64	62	96.88
CONT_ASSIGN	329	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
109	1	1
110	1	1
111	1	1
112	1	1
114	1	1
116	1	1
117	1	1
120	1	1
122	1	1
123	1	1
130	1	1
135	1	1
137	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	0	1
153	1	1
154	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
			==> MISSING_ELSE
187	1	1
190	2	2
191	1	1
195	1	1
196	1	1
198	1	1
199	1	1
201	1	1
202	1	1
204	1	1
205	1	1
207	1	1
209	1	1
211	1	1
212	1	1
213	1	1
215	1	1
217	1	1
218	1	1
220	1	1
221	1	1
222	1	1
223	1	1
225	1	1
230	1	1
232	1	1
233	1	1
235	1	1
237	1	1
239	1	1
244	1	1
245	1	1
247	1	1
248	0	1
249	0	1
			MISSING_ELSE
252	1	1
254	1	1
256	1	1
257	1	1
259	1	1
261	1	1
266	1	1
268	1	1
269	1	1
270	1	1
272	1	1
275	1	1
280	1	1
281	1	1
282	1	1
283	1	1
285	1	1
286	1	1
288	1	1
289	1	1
290	1	1
291	1	1
293	1	1
299	1	1
300	1	1
302	1	1
303	1	1
305	1	1
307	1	1
309	1	1
315	1	1
317	1	1
329	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	102	90	88.24
Logical	102	90	88.24
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       110
 EXPRESSION (hmac_en ? hash_continue : reg_hash_continue)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       112
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       120
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       120
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       120
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       122
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : ((sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       123
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? message_length : ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0))
                 -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (sel_msglen == SelIPadMsg)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)
                 -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T5

 LINE       130
 SUB-EXPRESSION (sel_msglen == SelOPadMsg)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T5

 LINE       135
 EXPRESSION (txcount[BlockSizeBits:0] == BlockSizeBSB)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       137
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       164
 EXPRESSION (hmac_hash_done || reg_hash_start || reg_hash_continue)
             -------1------    -------2------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T5

 LINE       182
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       187
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       187
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       245
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       247
 EXPRESSION ((round_q == Inner) && reg_hash_continue)
             ---------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Not Covered

 LINE       247
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       252
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       257
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       269
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       285
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
             -----1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       285
 SUB-EXPRESSION (fifo_wdata_sel == 3'h7)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       329
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start || reg_hash_continue) ))
             --------1-------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       329
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 SUB-EXPRESSION ( ! (reg_hash_start || reg_hash_continue) )
                    ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       329
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	270	Covered	T2,T3,T5
StIPad	218	Covered	T2,T3,T5
StIdle	225	Covered	T1,T2,T3
StMsg	233	Covered	T2,T3,T5
StOPad	286	Covered	T2,T3,T5
StPushToMsgFifo	272	Covered	T2,T3,T5
StWaitResp	254	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests
StDone->StIdle	315	Covered	T2,T3,T5
StIPad->StMsg	233	Covered	T2,T3,T5
StIdle->StIPad	218	Covered	T2,T3,T5
StMsg->StWaitResp	254	Covered	T2,T3,T5
StOPad->StMsg	303	Covered	T2,T3,T5
StPushToMsgFifo->StOPad	286	Covered	T2,T3,T5
StWaitResp->StDone	270	Covered	T2,T3,T5
StWaitResp->StPushToMsgFifo	272	Covered	T2,T3,T5

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		58	52	89.66
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	111	2	2	100.00
TERNARY	112	2	2	100.00
TERNARY	120	2	2	100.00
TERNARY	122	2	2	100.00
TERNARY	123	5	4	80.00
TERNARY	130	4	3	75.00
TERNARY	187	2	2	100.00
IF	145	5	4	80.00
IF	160	4	4	100.00
IF	170	3	3	100.00
IF	178	4	3	75.00
IF	190	2	2	100.00
CASE	215	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	120	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	((!hmac_en)) ? 
-2-:	123	((sel_rdata == SelIPad)) ? 
-3-:	123	((sel_rdata == SelOPad)) ? 
-4-:	123	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T5
0	0	1	-	Covered	T2,T3,T5
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	130	((!hmac_en)) ? 
-2-:	130	((sel_msglen == SelIPadMsg)) ? 
-3-:	130	((sel_msglen == SelOPadMsg)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T5
0	0	0	Not Covered

	LineNo.	Expression
-1-:	187	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	145	if ((!rst_ni))
-2-:	147	if (clr_txcount)
-3-:	149	if (load_txcount)
-4-:	153	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T5
0	0	1	-	Not Covered
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if (reg_hash_process)
-3-:	164	if (((hmac_hash_done || reg_hash_start) || reg_hash_continue))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	if ((!rst_ni))
-2-:	180	if (clr_fifo_wdata_sel)
-3-:	182	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Not Covered

	LineNo.	Expression
-1-:	190	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	case (st_q)
-2-:	217	if ((hmac_en && reg_hash_start))
-3-:	232	if (txcnt_eq_blksz)
-4-:	247	if (((round_q == Inner) && reg_hash_continue))
-5-:	252	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-6-:	268	if (sha_hash_done)
-7-:	269	if ((round_q == Outer))
-8-:	285	if ((fifo_wready && (fifo_wdata_sel == 3'h7)))
-9-:	302	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T2,T3,T5
StIPad	-	0	-	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	1	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	0	-	-	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	1	1	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	1	0	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	0	-	-	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	1	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
StDone	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
TOTAL		106	103	97.17
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	145	8	7	87.50
ALWAYS	160	6	6	100.00
ALWAYS	170	4	4	100.00
ALWAYS	178	6	6	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	3	3	100.00
ALWAYS	195	64	62	96.88
CONT_ASSIGN	329	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
109	1	1
110	1	1
111	1	1
112	1	1
114	1	1
116	1	1
117	1	1
120	1	1
122	1	1
123	1	1
130	1	1
135	1	1
137	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	0	1
153	1	1
154	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
			==> MISSING_ELSE
187	1	1
190	2	2
191	1	1
195	1	1
196	1	1
198	1	1
199	1	1
201	1	1
202	1	1
204	1	1
205	1	1
207	1	1
209	1	1
211	1	1
212	1	1
213	1	1
215	1	1
217	1	1
218	1	1
220	1	1
221	1	1
222	1	1
223	1	1
225	1	1
230	1	1
232	1	1
233	1	1
235	1	1
237	1	1
239	1	1
244	1	1
245	1	1
247	1	1
248	0	1
249	0	1
			MISSING_ELSE
252	1	1
254	1	1
256	1	1
257	1	1
259	1	1
261	1	1
266	1	1
268	1	1
269	1	1
270	1	1
272	1	1
275	1	1
280	1	1
281	1	1
282	1	1
283	1	1
285	1	1
286	1	1
288	1	1
289	1	1
290	1	1
291	1	1
293	1	1
299	1	1
300	1	1
302	1	1
303	1	1
305	1	1
307	1	1
309	1	1
315	1	1
317	1	1
			Exclude Annotation: VC_COV_UNR
329	1	1

---

Cond Coverage for Instance : tb.dut.u_hmac

	Total	Covered	Percent
Conditions	88	84	95.45
Logical	88	84	95.45
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       110
 EXPRESSION (hmac_en ? hash_continue : reg_hash_continue)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       112
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       120
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       120
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       120
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       122
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : ((sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       123
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       123
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       123
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? message_length : ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0))
                 -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (sel_msglen == SelIPadMsg)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)
                 -------------1------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T5

 LINE       130
 SUB-EXPRESSION (sel_msglen == SelOPadMsg)
                -------------1------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T5

 LINE       135
 EXPRESSION (txcount[BlockSizeBits:0] == BlockSizeBSB)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       137
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----
 Exclude Annotation: [UNR] sha_rready=1 requires sha_rvalid=1.

-1-	-2-	Status	Tests
0	1	Excluded	T2,T3,T4
1	0	Excluded
1	1	Excluded	T2,T3,T4

 LINE       164
 EXPRESSION (hmac_hash_done || reg_hash_start || reg_hash_continue)
             -------1------    -------2------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T5

 LINE       182
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       187
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       187
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       245
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       247
 EXPRESSION ((round_q == Inner) && reg_hash_continue)
             ---------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Not Covered

 LINE       247
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       252
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       252
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       257
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       269
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       285
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
             -----1-----    ------------2-----------
 Exclude Annotation: [UNR] tl_adapter with outstanding=1 drains fifo faster than it pushes. So it cannot have fifo full condition

 LINE       285
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
 Exclude Annotation: [UNR] tl_adapter with outstanding=1 drains fifo faster than it pushes. So it cannot have fifo full condition

-1-	-2-	Status	Tests
0	1	Excluded
1	0	Excluded	T2,T3,T5
1	1	Excluded	T2,T3,T5

 LINE       285
 SUB-EXPRESSION (fifo_wdata_sel == 3'h7)
                ------------1-----------

-1-	Status	Tests
0	Excluded	T2,T3,T5
1	Excluded	T2,T3,T5

 LINE       329
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start || reg_hash_continue) ))
             --------1-------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       329
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 SUB-EXPRESSION ( ! (reg_hash_start || reg_hash_continue) )
                    ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       329
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_hmac

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	270	Covered	T2,T3,T5
StIPad	218	Covered	T2,T3,T5
StIdle	225	Covered	T1,T2,T3
StMsg	233	Covered	T2,T3,T5
StOPad	286	Covered	T2,T3,T5
StPushToMsgFifo	272	Covered	T2,T3,T5
StWaitResp	254	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests
StDone->StIdle	315	Covered	T2,T3,T5
StIPad->StMsg	233	Covered	T2,T3,T5
StIdle->StIPad	218	Covered	T2,T3,T5
StMsg->StWaitResp	254	Covered	T2,T3,T5
StOPad->StMsg	303	Covered	T2,T3,T5
StPushToMsgFifo->StOPad	286	Covered	T2,T3,T5
StWaitResp->StDone	270	Covered	T2,T3,T5
StWaitResp->StPushToMsgFifo	272	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
Branches		55	52	94.55
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	111	2	2	100.00
TERNARY	112	2	2	100.00
TERNARY	120	2	2	100.00
TERNARY	122	2	2	100.00
TERNARY	123	4	4	100.00
TERNARY	130	3	3	100.00
TERNARY	187	2	2	100.00
IF	145	5	4	80.00
IF	160	4	4	100.00
IF	170	3	3	100.00
IF	178	3	3	100.00
IF	190	2	2	100.00
CASE	215	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	120	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	((!hmac_en)) ? 
-2-:	123	((sel_rdata == SelIPad)) ? 
-3-:	123	((sel_rdata == SelOPad)) ? 
-4-:	123	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T5
0	0	1	-	Covered	T2,T3,T5
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	130	((!hmac_en)) ? 
-2-:	130	((sel_msglen == SelIPadMsg)) ? 
-3-:	130	((sel_msglen == SelOPadMsg)) ? 

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T5
0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	187	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	145	if ((!rst_ni))
-2-:	147	if (clr_txcount)
-3-:	149	if (load_txcount)
-4-:	153	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T5
0	0	1	-	Not Covered
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if (reg_hash_process)
-3-:	164	if (((hmac_hash_done || reg_hash_start) || reg_hash_continue))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	if ((!rst_ni))
-2-:	180	if (clr_fifo_wdata_sel)
-3-:	182	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	190	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	case (st_q)
-2-:	217	if ((hmac_en && reg_hash_start))
-3-:	232	if (txcnt_eq_blksz)
-4-:	247	if (((round_q == Inner) && reg_hash_continue))
-5-:	252	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-6-:	268	if (sha_hash_done)
-7-:	269	if ((round_q == Outer))
-8-:	285	if ((fifo_wready && (fifo_wdata_sel == 3'h7)))
-9-:	302	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T2,T3,T5
StIPad	-	0	-	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	1	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	0	-	-	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	1	1	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	1	0	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	0	-	-	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	1	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
StDone	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	Not Covered