Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.18	100.00	96.72			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.18	100.00	96.72			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.18	100.00	96.72			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.08	99.50	97.51	100.00		98.39	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.56	95.03	84.62	100.00	40.00	87.69	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_continue	100.00	100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_cmd_hash_stop	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	62.59	77.78	50.00			60.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_2	100.00	100.00
u_key_3	100.00	100.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_msg_length_lower	100.00	100.00
u_msg_length_upper	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		244	244	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	825	1	1	100.00
CONT_ASSIGN	832	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	874	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	951	1	1	100.00
CONT_ASSIGN	958	1	1	100.00
CONT_ASSIGN	972	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	993	1	1	100.00
CONT_ASSIGN	1000	1	1	100.00
CONT_ASSIGN	1014	1	1	100.00
CONT_ASSIGN	1021	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1077	1	1	100.00
CONT_ASSIGN	1083	1	1	100.00
CONT_ASSIGN	1097	1	1	100.00
CONT_ASSIGN	1103	1	1	100.00
CONT_ASSIGN	1117	1	1	100.00
ALWAYS	1123	28	28	100.00
CONT_ASSIGN	1153	1	1	100.00
ALWAYS	1157	1	1	100.00
CONT_ASSIGN	1188	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1192	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1195	1	1	100.00
CONT_ASSIGN	1197	1	1	100.00
CONT_ASSIGN	1199	1	1	100.00
CONT_ASSIGN	1200	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1204	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1209	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1213	1	1	100.00
CONT_ASSIGN	1215	1	1	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1219	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1222	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1230	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1296	1	1	100.00
ALWAYS	1300	28	28	100.00
ALWAYS	1332	43	43	100.00
CONT_ASSIGN	1467	0	0
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
441	1	1
456	1	1
472	1	1
488	1	1
494	1	1
508	1	1
514	1	1
529	1	1
545	1	1
561	1	1
577	1	1
583	1	1
598	1	1
614	1	1
630	1	1
646	1	1
727	1	1
741	1	1
748	1	1
762	1	1
769	1	1
783	1	1
790	1	1
804	1	1
811	1	1
825	1	1
832	1	1
846	1	1
853	1	1
867	1	1
874	1	1
888	1	1
895	1	1
909	1	1
916	1	1
930	1	1
937	1	1
951	1	1
958	1	1
972	1	1
979	1	1
993	1	1
1000	1	1
1014	1	1
1021	1	1
1035	1	1
1042	1	1
1056	1	1
1063	1	1
1077	1	1
1083	1	1
1097	1	1
1103	1	1
1117	1	1
1123	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1153	1	1
1157	1	1
1188	1	1
1190	1	1
1192	1	1
1193	1	1
1195	1	1
1197	1	1
1199	1	1
1200	1	1
1202	1	1
1204	1	1
1206	1	1
1207	1	1
1209	1	1
1210	1	1
1211	1	1
1213	1	1
1215	1	1
1217	1	1
1219	1	1
1220	1	1
1222	1	1
1224	1	1
1226	1	1
1228	1	1
1229	1	1
1230	1	1
1232	1	1
1233	1	1
1235	1	1
1236	1	1
1238	1	1
1239	1	1
1241	1	1
1242	1	1
1244	1	1
1245	1	1
1247	1	1
1248	1	1
1250	1	1
1251	1	1
1253	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1260	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1266	1	1
1268	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1276	1	1
1277	1	1
1278	1	1
1280	1	1
1281	1	1
1282	1	1
1284	1	1
1285	1	1
1286	1	1
1288	1	1
1289	1	1
1290	1	1
1292	1	1
1293	1	1
1294	1	1
1296	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1332	1	1
1333	1	1
1335	1	1
1336	1	1
1337	1	1
1341	1	1
1342	1	1
1343	1	1
1347	1	1
1348	1	1
1349	1	1
1353	1	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1364	1	1
1365	1	1
1366	1	1
1367	1	1
1371	1	1
1372	1	1
1373	1	1
1377	1	1
1381	1	1
1385	1	1
1389	1	1
1393	1	1
1397	1	1
1401	1	1
1405	1	1
1409	1	1
1413	1	1
1417	1	1
1421	1	1
1425	1	1
1429	1	1
1433	1	1
1437	1	1
1441	1	1
1445	1	1
1449	1	1
1453	1	1
1467		unreachable
1475	1	1
1476	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	335	324	96.72
Logical	335	324	96.72
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16,T17
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T23,T24
1	0	Covered	T44,T45,T46

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T23,T24
0	1	0	Covered	T44,T45,T46
1	0	0	Covered	T10,T23,T24

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T46
0	1	0	Covered	T15,T16,T17
1	0	0	Covered	T15,T16,T17

 LINE       1124
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1125
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1126
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       1127
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       1128
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CFG_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1129
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1130
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1131
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1132
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       1133
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1134
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1135
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1136
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1137
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1138
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_5_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1139
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_6_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1140
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_KEY_7_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1141
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1142
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1143
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1144
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1145
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1146
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1147
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1148
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_DIGEST_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1149
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1150
 EXPRESSION (reg_addr == hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1153
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1153
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1157
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T17

 LINE       1157
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
27 (addr_hit[26] & ((|(4'...	Covered	T1,T2,T3
26 (addr_hit[25] & ((|(4'...	Covered	T1,T2,T3
25 (addr_hit[24] & ((|(4'...	Covered	T1,T2,T3
24 (addr_hit[23] & ((|(4'...	Covered	T1,T2,T3
23 (addr_hit[22] & ((|(4'...	Covered	T1,T2,T3
22 (addr_hit[21] & ((|(4'...	Covered	T1,T2,T3
21 (addr_hit[20] & ((|(4'...	Covered	T1,T2,T3
20 (addr_hit[19] & ((|(4'...	Covered	T1,T2,T3
19 (addr_hit[18] & ((|(4'...	Covered	T1,T2,T3
18 (addr_hit[17] & ((|(4'...	Covered	T1,T2,T3
17 (addr_hit[16] & ((|(4'...	Covered	T2,T3,T14
16 (addr_hit[15] & ((|(4'...	Covered	T2,T3,T14
15 (addr_hit[14] & ((|(4'...	Covered	T2,T3,T14
14 (addr_hit[13] & ((|(4'...	Covered	T2,T3,T14
13 (addr_hit[12] & ((|(4'...	Covered	T2,T3,T14
12 (addr_hit[11] & ((|(4'...	Covered	T2,T3,T14
11 (addr_hit[10] & ((|(4'...	Covered	T2,T3,T14
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T3,T14
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T3,T14
8 (addr_hit[7] & ((|(4'b...	Covered	T1,T2,T3
7 (addr_hit[6] & ((|(4'b...	Covered	T1,T2,T3
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T3,T14
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T3,T14
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T3,T14
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T3,T14
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T3,T14
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       1157
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1157
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1188
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1193
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1200
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T11,T12,T15

 LINE       1207
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T7,T8,T9

 LINE       1210
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T47
1	1	1	Covered	T15,T16,T17

 LINE       1211
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1220
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1229
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1230
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T5,T19,T12

 LINE       1233
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1236
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1239
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1242
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1245
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1248
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1251
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1254
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1257
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1258
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1261
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1262
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1265
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1266
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1269
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1270
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1273
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1274
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1277
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1278
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1281
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1282
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1285
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1286
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1289
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1290
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

 LINE       1293
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       1294
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T17
1	1	1	Covered	T48,T44,T45

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		37	37	100.00
TERNARY	1153	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1333	28	28	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1153	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T23,T24
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1333	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	448419016	56929601	0	0
reAfterRv	448419016	56929601	0	0
rePulse	448419016	31465833	0	0
wePulse	448419016	25463768	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	56929601	0	0
T1	100968	75930	0	0
T2	230721	90534	0	0
T3	109022	125545	0	0
T4	153372	2122	0	0
T5	132303	30202	0	0
T13	433617	336908	0	0
T14	228144	249081	0	0
T20	7217	451	0	0
T21	11911	1945	0	0
T22	4252	232	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	56929601	0	0
T1	100968	75930	0	0
T2	230721	90534	0	0
T3	109022	125545	0	0
T4	153372	2122	0	0
T5	132303	30202	0	0
T13	433617	336908	0	0
T14	228144	249081	0	0
T20	7217	451	0	0
T21	11911	1945	0	0
T22	4252	232	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	31465833	0	0
T1	100968	43446	0	0
T2	230721	52238	0	0
T3	109022	68602	0	0
T4	153372	1522	0	0
T5	132303	20215	0	0
T13	433617	171541	0	0
T14	228144	131387	0	0
T20	7217	211	0	0
T21	11911	1341	0	0
T22	4252	103	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	25463768	0	0
T1	100968	32484	0	0
T2	230721	38296	0	0
T3	109022	56943	0	0
T4	153372	600	0	0
T5	132303	9987	0	0
T13	433617	165367	0	0
T14	228144	117694	0	0
T20	7217	240	0	0
T21	11911	604	0	0
T22	4252	129	0	0