Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.67	95.03	79.28	100.00	40.00	87.69	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	84.56	95.03	84.62	100.00	40.00	87.69	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.56	95.03	84.62	100.00	40.00	87.69	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18	98.23	96.36	100.00	87.50	95.49	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	96.79	97.17	95.45		100.00	94.55
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_256	94.82	96.46	94.87		94.74	93.22
u_reg	99.08	99.50	97.51	100.00		98.39	100.00
u_tlul_adapter	97.46	98.54	100.00			98.44	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		161	153	95.03
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	136	15	9	60.00
ALWAYS	178	3	3	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	8	8	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	6	6	100.00
ALWAYS	254	4	4	100.00
ALWAYS	269	6	6	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	337	5	5	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
ALWAYS	450	3	3	100.00
ALWAYS	458	11	9	81.82
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
ALWAYS	631	6	6	100.00
CONT_ASSIGN	647	1	1	100.00
ALWAYS	652	6	6	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
ALWAYS	704	3	3	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	732	6	6	100.00
ALWAYS	739	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
124	1	1
136	1	1
137	1	1
139	1	1
141	1	1
143	1	1
144	1	1
146	0	1
			MISSING_ELSE
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
158	0	1
162	0	1
			==> MISSING_ELSE
167	0	1
168	0	1
169	0	1
			==> MISSING_ELSE
178	1	1
179	1	1
181	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
			MISSING_ELSE
207	8	8
209	8	8
210	8	8
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
230	1	1
233	1	1
234	1	1
239	1	1
240	1	1
241	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
254	1	1
255	1	1
262	1	1
263	1	1
			MISSING_ELSE
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
317	1	1
324	1	1
332	1	1
334	1	1
337	1	1
338	1	1
339	1	1
341	1	1
342	1	1
378	1	1
381	1	1
385	1	1
386	1	1
388	1	1
389	1	1
390	1	1
391	1	1
445	1	1
450	1	1
451	1	1
452	1	1
458	1	1
459	1	1
461	1	1
462	1	1
463	0	1
			MISSING_ELSE
465	1	1
466	0	1
			MISSING_ELSE
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE
477	1	1
478	1	1
486	1	1
487	1	1
598	1	1
626	1	1
627	1	1
628	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
			MISSING_ELSE
639	1	1
647	1	1
652	1	1
653	1	1
655	1	1
659	1	1
663	1	1
667	1	1
680	1	1
698	1	1
702	1	1
704	1	1
705	1	1
707	1	1
710	1	1
732	2	2
733	2	2
734	2	2
			MISSING_ELSE
739	2	2
740	2	2
741	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	111	88	79.28
Logical	111	88	79.28
Non-Logical	0	0
Event	0	0

 LINE       158
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       227
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       229
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       230
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       241
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       332
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       381
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       390
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       390
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       445
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       471
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       493
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       493
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       598
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       626
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       626
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       627
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       627
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       628
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       647
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       647
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3

 LINE       698
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T7,T8	Yes	T10,T7,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T7,T8	Yes	T10,T7,T8	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	153	Covered	T1,T2,T3
DoneAwaitHashComplete	162	Not Covered
DoneAwaitHashDone	143	Covered	T1,T2,T3
DoneAwaitMessageComplete	146	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	143	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	146	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	169	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	153	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	162	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		65	57	87.69
TERNARY	324	4	4	100.00
TERNARY	334	2	2	100.00
TERNARY	390	2	2	100.00
TERNARY	391	2	2	100.00
CASE	139	10	4	40.00
IF	178	2	2	100.00
IF	190	4	4	100.00
IF	244	4	4	100.00
IF	254	3	3	100.00
IF	269	4	4	100.00
IF	337	2	2	100.00
IF	458	9	7	77.78
IF	632	2	2	100.00
CASE	653	5	5	100.00
IF	704	2	2	100.00
IF	732	4	4	100.00
IF	739	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	324	(fifo_full) ? 
-2-:	324	(fifo_empty_negedge) ? 
-3-:	324	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	390	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	case (done_state_q)
-2-:	141	if (sha_hash_process)
-3-:	144	if (reg_hash_stop)
-4-:	151	if (reg_hash_done)
-5-:	158	if ((sha_message_length[8:0] == '0))
-6-:	167	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	178	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	if ((!rst_ni))
-2-:	192	if (wipe_secret)
-3-:	194	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T19,T12
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if ((!rst_ni))
-2-:	246	if (hash_start_or_continue)
-3-:	248	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	if ((!rst_ni))
-2-:	262	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	if ((!rst_ni))
-2-:	271	if (hash_start_or_continue)
-3-:	273	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	458	if ((!rst_ni))
-2-:	461	if ((!cfg_block))
-3-:	462	if (reg2hw.msg_length_lower.qe)
-4-:	465	if (reg2hw.msg_length_upper.qe)
-5-:	469	if (hash_start)
-6-:	471	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	632	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	653	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T1,T2,T3
hash_start_active	Covered	T1,T2,T3
msg_push_not_allowed	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	704	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	732	if ((!rst_ni))
-2-:	733	if (reg_hash_process)
-3-:	734	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	if ((!rst_ni))
-2-:	740	if (hash_start_or_continue)
-3-:	741	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	447573117	447502180	0	0
FpvSecCmRegWeOnehotCheck_A	447573117	100	0	0
IntrFifoEmptyOKnown	447573117	447502180	0	0
IntrHmacDoneOKnown	447573117	447502180	0	0
TlOAReadyKnown	447573117	447502180	0	0
TlODValidKnown	447573117	447502180	0	0
ValidHashProcessAssert	447573117	44509	0	0
ValidHmacEnConditionAssert	447573117	10463	0	0
ValidWriteAssert	447573117	24537623	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	447573117	24537623	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	100	0	0
T7	1320	0	0	0
T10	6670	20	0	0
T18	135978	0	0	0
T19	138457	0	0	0
T23	0	10	0	0
T24	0	30	0	0
T25	0	20	0	0
T26	0	20	0	0
T27	16177	0	0	0
T28	287485	0	0	0
T29	743256	0	0	0
T30	140808	0	0	0
T31	713210	0	0	0
T32	48806	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	44509	0	0
T1	100968	7	0	0
T2	230721	8	0	0
T3	109022	11	0	0
T4	153372	46	0	0
T5	132303	37	0	0
T13	433617	194	0	0
T14	228144	194	0	0
T20	7217	4	0	0
T21	11911	34	0	0
T22	4252	4	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	10463	0	0
T1	100968	9	0	0
T2	230721	15	0	0
T3	109022	35	0	0
T4	153372	22	0	0
T5	132303	19	0	0
T6	0	1	0	0
T13	433617	0	0	0
T14	228144	0	0	0
T19	0	5	0	0
T20	7217	1	0	0
T21	11911	18	0	0
T22	4252	1	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	153	95.03
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	136	15	9	60.00
ALWAYS	178	3	3	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	8	8	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	6	6	100.00
ALWAYS	254	4	4	100.00
ALWAYS	269	6	6	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	337	5	5	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
ALWAYS	450	3	3	100.00
ALWAYS	458	11	9	81.82
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
ALWAYS	631	6	6	100.00
CONT_ASSIGN	647	1	1	100.00
ALWAYS	652	6	6	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
ALWAYS	704	3	3	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	732	6	6	100.00
ALWAYS	739	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
124	1	1
136	1	1
137	1	1
139	1	1
141	1	1
143	1	1
144	1	1
146	0	1
			MISSING_ELSE
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
158	0	1
162	0	1
			==> MISSING_ELSE
167	0	1
168	0	1
169	0	1
			==> MISSING_ELSE
178	1	1
179	1	1
181	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
			MISSING_ELSE
207	8	8
209	8	8
210	8	8
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
230	1	1
233	1	1
234	1	1
239	1	1
240	1	1
241	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
254	1	1
255	1	1
262	1	1
263	1	1
			MISSING_ELSE
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
317	1	1
324	1	1
332	1	1
334	1	1
337	1	1
338	1	1
339	1	1
341	1	1
342	1	1
378	1	1
381	1	1
385	1	1
386	1	1
388	1	1
389	1	1
390	1	1
391	1	1
445	1	1
450	1	1
451	1	1
452	1	1
458	1	1
459	1	1
461	1	1
462	1	1
463	0	1
			MISSING_ELSE
465	1	1
466	0	1
			MISSING_ELSE
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE
477	1	1
478	1	1
486	1	1
487	1	1
598	1	1
626	1	1
627	1	1
628	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
			MISSING_ELSE
639	1	1
647	1	1
652	1	1
653	1	1
655	1	1
659	1	1
663	1	1
667	1	1
680	1	1
698	1	1
702	1	1
704	1	1
705	1	1
707	1	1
710	1	1
732	2	2
733	2	2
734	2	2
			MISSING_ELSE
739	2	2
740	2	2
741	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	104	88	84.62
Logical	104	88	84.62
Non-Logical	0	0
Event	0	0

 LINE       158
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       227
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       229
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       230
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       241
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       262
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       332
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       381
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       390
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       390
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (hmac_fifo_wsel ? ('{data:digest[hmac_fifo_wdata_sel][31:0], mask:'1}) : reg_fifo_wentry)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       445
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       471
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Unreachable	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       493
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       493
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       598
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       626
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       626
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       627
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       627
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       628
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       647
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       647
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3

 LINE       698
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T13	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T7,T8	Yes	T10,T7,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T7,T8	Yes	T10,T7,T8	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	153	Covered	T1,T2,T3
DoneAwaitHashComplete	162	Not Covered
DoneAwaitHashDone	143	Covered	T1,T2,T3
DoneAwaitMessageComplete	146	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	143	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	146	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	169	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	153	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	162	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	57	87.69
TERNARY	324	4	4	100.00
TERNARY	334	2	2	100.00
TERNARY	390	2	2	100.00
TERNARY	391	2	2	100.00
CASE	139	10	4	40.00
IF	178	2	2	100.00
IF	190	4	4	100.00
IF	244	4	4	100.00
IF	254	3	3	100.00
IF	269	4	4	100.00
IF	337	2	2	100.00
IF	458	9	7	77.78
IF	632	2	2	100.00
CASE	653	5	5	100.00
IF	704	2	2	100.00
IF	732	4	4	100.00
IF	739	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	324	(fifo_full) ? 
-2-:	324	(fifo_empty_negedge) ? 
-3-:	324	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	390	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(hmac_fifo_wsel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	case (done_state_q)
-2-:	141	if (sha_hash_process)
-3-:	144	if (reg_hash_stop)
-4-:	151	if (reg_hash_done)
-5-:	158	if ((sha_message_length[8:0] == '0))
-6-:	167	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	178	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	if ((!rst_ni))
-2-:	192	if (wipe_secret)
-3-:	194	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T19,T12
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if ((!rst_ni))
-2-:	246	if (hash_start_or_continue)
-3-:	248	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	if ((!rst_ni))
-2-:	262	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	if ((!rst_ni))
-2-:	271	if (hash_start_or_continue)
-3-:	273	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	458	if ((!rst_ni))
-2-:	461	if ((!cfg_block))
-3-:	462	if (reg2hw.msg_length_lower.qe)
-4-:	465	if (reg2hw.msg_length_upper.qe)
-5-:	469	if (hash_start)
-6-:	471	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	632	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	653	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T1,T2,T3
hash_start_active	Covered	T1,T2,T3
msg_push_not_allowed	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	704	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	732	if ((!rst_ni))
-2-:	733	if (reg_hash_process)
-3-:	734	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	if ((!rst_ni))
-2-:	740	if (hash_start_or_continue)
-3-:	741	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	447573117	447502180	0	0
FpvSecCmRegWeOnehotCheck_A	447573117	100	0	0
IntrFifoEmptyOKnown	447573117	447502180	0	0
IntrHmacDoneOKnown	447573117	447502180	0	0
TlOAReadyKnown	447573117	447502180	0	0
TlODValidKnown	447573117	447502180	0	0
ValidHashProcessAssert	447573117	44509	0	0
ValidHmacEnConditionAssert	447573117	10463	0	0
ValidWriteAssert	447573117	24537623	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	447573117	24537623	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	447573117	24537623	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	100	0	0
T7	1320	0	0	0
T10	6670	20	0	0
T18	135978	0	0	0
T19	138457	0	0	0
T23	0	10	0	0
T24	0	30	0	0
T25	0	20	0	0
T26	0	20	0	0
T27	16177	0	0	0
T28	287485	0	0	0
T29	743256	0	0	0
T30	140808	0	0	0
T31	713210	0	0	0
T32	48806	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	447502180	0	0
T1	100968	100961	0	0
T2	230721	230623	0	0
T3	109022	109012	0	0
T4	153372	153287	0	0
T5	132303	132232	0	0
T13	433617	433608	0	0
T14	228144	228134	0	0
T20	7217	7131	0	0
T21	11911	11840	0	0
T22	4252	4168	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	44509	0	0
T1	100968	7	0	0
T2	230721	8	0	0
T3	109022	11	0	0
T4	153372	46	0	0
T5	132303	37	0	0
T13	433617	194	0	0
T14	228144	194	0	0
T20	7217	4	0	0
T21	11911	34	0	0
T22	4252	4	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	10463	0	0
T1	100968	9	0	0
T2	230721	15	0	0
T3	109022	35	0	0
T4	153372	22	0	0
T5	132303	19	0	0
T6	0	1	0	0
T13	433617	0	0	0
T14	228144	0	0	0
T19	0	5	0	0
T20	7217	1	0	0
T21	11911	18	0	0
T22	4252	1	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	447573117	24537623	0	0
T1	100968	20425	0	0
T2	230721	22632	0	0
T3	109022	30670	0	0
T4	153372	108442	0	0
T5	132303	19127	0	0
T13	433617	74159	0	0
T14	228144	74217	0	0
T20	7217	53	0	0
T21	11911	316	0	0
T22	4252	50	0	0