Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.56	95.03	84.62	100.00	40.00	87.69	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	448419016	2312398	0	0
intr_enable_rd_A	448419016	2779	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	2312398	0	0
T15	125380	50500	0	0
T16	0	141622	0	0
T17	0	233070	0	0
T33	0	252883	0	0
T34	0	388362	0	0
T36	0	664584	0	0
T49	0	20210	0	0
T50	0	22874	0	0
T51	0	119853	0	0
T52	0	69936	0	0
T53	196763	0	0	0
T54	54320	0	0	0
T55	873585	0	0	0
T56	349698	0	0	0
T57	12670	0	0	0
T58	891919	0	0	0
T59	686990	0	0	0
T60	780292	0	0	0
T61	3933	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448419016	2779	0	0
T12	185374	12	0	0
T15	125380	0	0	0
T53	196763	0	0	0
T54	54320	0	0	0
T55	873585	0	0	0
T56	349698	0	0	0
T57	12670	0	0	0
T58	891919	43	0	0
T59	686990	0	0	0
T62	0	51	0	0
T63	0	38	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	0	12	0	0
T67	0	29	0	0
T68	0	45	0	0
T69	0	35	0	0
T70	128306	0	0	0