Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45160556

1

T1

46

T2

268

T3

39334

full_word

42595792

1

T1

63

T2

290

T3

40487

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87755908	1			T1	109		T2	558		T3	79821
auto[TlIntgErrCmd]	135	1			T54	7		T55	9		T56	2
auto[TlIntgErrData]	158	1			T54	12		T55	8		T56	5
auto[TlIntgErrBoth]	147	1			T54	11		T55	13		T56	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34517604

1

T1

44

T2

249

T3

34827

auto[1]

53238744

1

T1

65

T2

309

T3

44994

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18683690	1			T1	21		T2	126		T3	17406
auto[TlIntgErrNone]	partial	auto[1]	26476459	1			T1	25		T2	142		T3	21928
auto[TlIntgErrNone]	full_word	auto[0]	15833728	1			T1	23		T2	123		T3	17421
auto[TlIntgErrNone]	full_word	auto[1]	26762031	1			T1	40		T2	167		T3	23066
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T54	5		T55	3		T56	1
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T54	2		T55	5		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T109	1		T60	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T55	1		T104	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T54	6		T55	3		T56	2
auto[TlIntgErrData]	partial	auto[1]	73	1			T54	5		T55	5		T56	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T54	1		T110	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T56	1		T110	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T54	5		T55	5		T56	2
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T54	6		T55	8		T56	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T106	1		T108	1		T61	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T106	2		T110	1		T107	2