Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	463155613	3227422	0	0
intr_enable_rd_A	463155613	4377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463155613	3227422	0	0
T10	707736	194419	0	0
T11	0	182691	0	0
T12	0	92415	0	0
T13	685289	309818	0	0
T14	0	186854	0	0
T15	0	50081	0	0
T21	31728	0	0	0
T36	0	198394	0	0
T52	282397	0	0	0
T53	57516	0	0	0
T63	0	39960	0	0
T64	0	113777	0	0
T65	0	256527	0	0
T66	352235	0	0	0
T67	11706	0	0	0
T68	245180	0	0	0
T69	3978	0	0	0
T70	86335	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463155613	4377	0	0
T10	707736	64	0	0
T17	0	52	0	0
T21	31728	0	0	0
T66	352235	0	0	0
T67	11706	0	0	0
T68	245180	0	0	0
T69	3978	0	0	0
T70	86335	0	0	0
T71	0	72	0	0
T72	0	25	0	0
T73	0	21	0	0
T74	0	9	0	0
T75	0	42	0	0
T76	0	9	0	0
T77	0	13	0	0
T78	0	17	0	0
T79	304706	0	0	0
T80	244613	0	0	0
T81	123810	0	0	0