Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.20	58.00	45.07			59.52

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512	54.20	58.00	45.07			59.52

---

Module Instance : tb.dut.u_prim_sha2_512

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.20	58.00	45.07			59.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.73	80.49	53.67		72.00	72.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_multimode_logic.u_prim_sha2_multimode	73.32	88.85	55.93		72.00	76.51

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		100	58	58.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	61	87	45	51.72
ALWAYS	225	3	3	100.00
ALWAYS	230	3	3	100.00
ALWAYS	235	3	3	100.00
ALWAYS	240	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
70	2	2
71	1	1
73	1	1
74	1	1
75	1	1
77	0	1
78	0	1
79	0	1
80	0	1
96	1	1
98	1	1
99	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
107	1	1
109	1	1
111	1	1
114	0	1
115	0	1
117	0	1
118	0	1
121	0	1
122	0	1
123	0	1
124	0	1
125	0	1
127	0	1
128	0	1
			==> MISSING_ELSE
130	0	1
132	0	1
133	0	1
134	0	1
136	0	1
137	0	1
139	0	1
141	0	1
142	0	1
143	0	1
144	0	1
145	0	1
			==> MISSING_ELSE
147	0	1
149	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
152	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	0	1
160	0	1
161	0	1
162	0	1
163	0	1
164	0	1
			==> MISSING_ELSE
166	1	1
167	0	1
168	1	1
170	0	1
171	0	1
172	0	1
173	0	1
			==> MISSING_ELSE
175	1	1
176	0	1
			MISSING_ELSE
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	0	1
186	1	1
190	2	2
191	2	2
192	1	1
195	2	2
196	2	2
197	1	1
225	2	2
226	1	1
230	2	2
231	1	1
235	2	2
236	1	1
240	2	2
241	1	1

---

Cond Coverage for Module : prim_sha2_32

	Total	Covered	Percent
Conditions	71	32	45.07
Logical	71	32	45.07
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       104
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       127
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       130
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       139
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       147
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       157
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       157
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       157
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       163
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       166
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       168
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       168
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       168
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       172
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       175
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       181
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Not Covered

 LINE       195
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
Branches		42	25	59.52
IF	70	2	2	100.00
IF	73	23	7	30.43
IF	181	3	2	66.67
IF	190	3	3	100.00
IF	195	3	3	100.00
IF	225	2	2	100.00
IF	230	2	2	100.00
IF	235	2	2	100.00
IF	240	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((sha_en_i && fifo_rvalid_i))
-2-:	74	if ((gen_multimode_logic.word_part_count_q == 2'b0))
-3-:	75	if ((gen_multimode_logic.digest_mode_flag_q != SHA2_256))
-4-:	104	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-5-:	107	if ((sha_ready == 1'b1))
-6-:	114	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-7-:	127	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-8-:	130	if ((sha_ready == 1'b1))
-9-:	139	if ((gen_multimode_logic.word_part_count_q == 2'b10))
-10-:	144	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-11-:	147	if ((sha_ready == 1'b1))
-12-:	152	if (sha_en_i)
-13-:	155	if (((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-14-:	157	if (((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-15-:	163	if ((sha_ready == 1'b1))
-16-:	166	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-17-:	168	if (((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-18-:	172	if ((sha_ready == 1'b1))
-19-:	175	if ((gen_multimode_logic.word_part_count_q == 2'b10))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	181	if (((gen_multimode_logic.word_part_reset || hash_go) || (!sha_en_i)))
-2-:	183	if (gen_multimode_logic.word_part_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	if (hash_go)
-2-:	191	if (hash_done_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	195	if (((!sha_en_i) || hash_go))
-2-:	196	if (hash_process_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3