Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.60	93.44	73.91	100.00	40.00	88.24	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	83.26	93.44	77.86	100.00	40.00	88.24	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.26	93.44	77.86	100.00	40.00	88.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.89	92.34	85.07	100.00	76.32	86.11	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	89.80	94.52	78.01		100.00	86.67
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	70.73	80.49	53.67		76.00	72.77
u_reg	98.20	94.80	97.48	100.00		98.72	100.00
u_tlul_adapter	88.93	93.95	89.16			79.75	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		183	171	93.44
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	143	15	9	60.00
ALWAYS	185	3	3	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	197	8	8	100.00
ALWAYS	220	0	0
ALWAYS	220	23	23	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
ALWAYS	271	5	5	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	284	6	6	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
ALWAYS	322	6	6	100.00
ALWAYS	332	4	4	100.00
ALWAYS	367	6	6	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	499	8	4	50.00
CONT_ASSIGN	568	1	1	100.00
ALWAYS	573	3	3	100.00
ALWAYS	581	12	10	83.33
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
ALWAYS	753	6	6	100.00
CONT_ASSIGN	769	1	1	100.00
ALWAYS	774	6	6	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
ALWAYS	817	3	3	100.00
CONT_ASSIGN	823	1	1	100.00
ALWAYS	845	6	6	100.00
ALWAYS	852	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
129	1	1
130	1	1
131	1	1
143	1	1
144	1	1
146	1	1
148	1	1
150	1	1
151	1	1
153	0	1
			MISSING_ELSE
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	0	1
169	0	1
			==> MISSING_ELSE
174	0	1
175	0	1
176	0	1
			==> MISSING_ELSE
185	1	1
186	1	1
188	1	1
193	1	1
194	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
			MISSING_ELSE
220	1	1
222	1	1
223	1	1
224	1	1
			MISSING_ELSE
227	1	1
228	1	1
230	1	1
232	1	1
233	1	1
235	1	1
237	1	1
238	1	1
240	1	1
241	1	1
243	1	1
244	1	1
246	1	1
247	1	1
249	1	1
250	1	1
253	1	1
255	1	1
256	1	1
262	1	1
266	1	1
267	1	1
269	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
282	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
295	1	1
296	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
307	1	1
308	1	1
311	1	1
312	1	1
317	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
			MISSING_ELSE
332	1	1
333	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
415	1	1
422	1	1
430	1	1
432	1	1
435	1	1
436	1	1
437	1	1
439	1	1
440	1	1
476	1	1
479	1	1
485	1	1
490	1	1
491	1	1
493	1	1
494	1	1
495	1	1
499	1	1
500	1	1
502	1	1
503	0	1
505	0	1
506	0	1
508	0	1
511	1	1
568	1	1
573	1	1
574	1	1
575	1	1
581	1	1
582	1	1
584	1	1
585	1	1
586	0	1
			MISSING_ELSE
588	1	1
589	0	1
			MISSING_ELSE
591	1	1
			MISSING_ELSE
593	1	1
594	1	1
595	1	1
596	1	1
			MISSING_ELSE
601	1	1
602	1	1
609	1	1
610	1	1
720	1	1
748	1	1
749	1	1
750	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
			MISSING_ELSE
761	1	1
769	1	1
774	1	1
775	1	1
777	1	1
781	1	1
785	1	1
789	1	1
811	1	1
815	1	1
817	1	1
818	1	1
820	1	1
823	1	1
845	2	2
846	2	2
847	2	2
			MISSING_ELSE
852	2	2
853	2	2
854	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	138	102	73.91
Logical	138	102	73.91
Non-Logical	0	0
Event	0	0

 LINE       165
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       227
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T8,T15

 LINE       237
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T15

 LINE       237
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T17

 LINE       238
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Not Covered
1	1	Covered	T2,T8,T15

 LINE       238
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T2,T8,T15
1	Covered	T2,T8,T15

 LINE       244
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T15
0	1	Not Covered
1	0	Not Covered

 LINE       250
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T15
0	1	Not Covered
1	0	Not Covered

 LINE       305
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       307
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       308
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T15,T18
1	1	0	Covered	T2,T8,T15
1	1	1	Covered	T1,T2,T3

 LINE       318
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       319
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       326
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       360
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       415
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       432
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       479
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T20,T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       495
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       495
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       500
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       503
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       521
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T2,T8,T15
1	1	1	1	Covered	T1,T2,T3

 LINE       595
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T20,T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       720
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       748
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T18

 LINE       748
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       749
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       749
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       750
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       769
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       769
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T8,T15
0	0	1	0	Covered	T2,T8,T15
0	1	0	0	Covered	T8,T15,T18
1	0	0	0	Covered	T8,T15,T18

 LINE       811
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T19,T26,T17	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T6,T27	Yes	T2,T6,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T9,T10,T13	Yes	T9,T10,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T19,T26,T17	Yes	T19,T26,T17	OUTPUT
intr_hmac_err_o	Yes	Yes	T2,T8,T19	Yes	T2,T8,T19	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitHashComplete	169	Not Covered
DoneAwaitHashDone	150	Covered	T1,T2,T3
DoneAwaitMessageComplete	153	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	150	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	153	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	176	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	169	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		85	75	88.24
TERNARY	422	4	4	100.00
TERNARY	432	2	2	100.00
TERNARY	495	2	2	100.00
CASE	146	10	4	40.00
IF	185	2	2	100.00
IF	197	4	4	100.00
IF	222	2	2	100.00
IF	227	5	5	100.00
CASE	271	5	5	100.00
CASE	284	6	6	100.00
IF	322	4	4	100.00
IF	332	3	3	100.00
IF	367	4	4	100.00
IF	435	2	2	100.00
IF	499	4	2	50.00
IF	581	9	7	77.78
IF	754	2	2	100.00
CASE	775	5	5	100.00
IF	817	2	2	100.00
IF	845	4	4	100.00
IF	852	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	422	(fifo_full) ? 
-2-:	422	(fifo_empty_negedge) ? 
-3-:	422	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	432	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	495	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	case (done_state_q)
-2-:	148	if (sha_hash_process)
-3-:	151	if (reg_hash_stop)
-4-:	158	if (reg_hash_done)
-5-:	165	if ((sha_message_length[8:0] == '0))
-6-:	174	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	185	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	if ((!rst_ni))
-2-:	199	if (wipe_secret)
-3-:	201	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T27,T19
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((digest_size == SHA2_256))
-2-:	228	if ((i < 8))
-3-:	237	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-:	238	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T3
1	0	-	-	Covered	T1,T2,T3
0	-	1	1	Covered	T2,T8,T15
0	-	1	0	Covered	T2,T8,T15
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T2,T8,T15
SHA2_512	Covered	T15,T16,T17
SHA2_None	Covered	T1,T2,T3
default	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	284	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T26,T29,T30
Key_256	Covered	T1,T2,T3
Key_384	Covered	T8,T16,T30
Key_512	Covered	T19,T26,T17
Key_1024	Covered	T17,T31,T32
default	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	322	if ((!rst_ni))
-2-:	324	if (hash_start_or_continue)
-3-:	326	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	if ((!rst_ni))
-2-:	360	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))
-2-:	369	if (hash_start_or_continue)
-3-:	371	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	435	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if (hmac_fifo_wsel)
-2-:	500	if ((digest_size == SHA2_256))
-3-:	503	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	581	if ((!rst_ni))
-2-:	584	if ((!cfg_block))
-3-:	585	if (reg2hw.msg_length_lower.qe)
-4-:	588	if (reg2hw.msg_length_upper.qe)
-5-:	593	if (hash_start)
-6-:	595	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	754	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T8,T15,T18
update_seckey_inprocess	Covered	T8,T15,T18
hash_start_active	Covered	T2,T8,T15
msg_push_not_allowed	Covered	T2,T8,T15
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	817	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	845	if ((!rst_ni))
-2-:	846	if (reg_hash_process)
-3-:	847	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	852	if ((!rst_ni))
-2-:	853	if (hash_start_or_continue)
-3-:	854	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	344283432	344213468	0	0
FpvSecCmRegWeOnehotCheck_A	344283432	110	0	0
IntrFifoEmptyOKnown	344283432	344213468	0	0
IntrHmacDoneOKnown	344283432	344213468	0	0
TlOAReadyKnown	344283432	344213468	0	0
TlODValidKnown	344283432	344213468	0	0
ValidHashProcessAssert	344283432	35941	0	0
ValidHmacEnConditionAssert	344283432	9300	0	0
ValidWriteAssert	344283432	19803741	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	344283432	19803741	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	110	0	0
T33	3817	10	0	0
T34	0	20	0	0
T35	0	20	0	0
T36	0	30	0	0
T37	0	30	0	0
T38	355192	0	0	0
T39	137388	0	0	0
T40	4735	0	0	0
T41	397908	0	0	0
T42	127874	0	0	0
T43	500524	0	0	0
T44	136722	0	0	0
T45	16413	0	0	0
T46	2681	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	35941	0	0
T1	16922	39	0	0
T2	278464	4	0	0
T3	87914	8	0	0
T4	174794	44	0	0
T5	12192	28	0	0
T6	850445	38	0	0
T7	639830	34	0	0
T8	553065	7	0	0
T27	131913	44	0	0
T28	36283	3	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	9300	0	0
T1	16922	18	0	0
T2	278464	15	0	0
T3	87914	2	0	0
T4	174794	22	0	0
T5	12192	16	0	0
T6	850445	19	0	0
T7	639830	22	0	0
T8	553065	13	0	0
T27	131913	25	0	0
T28	36283	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		183	171	93.44
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	143	15	9	60.00
ALWAYS	185	3	3	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	197	8	8	100.00
ALWAYS	220	0	0
ALWAYS	220	23	23	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
ALWAYS	271	5	5	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	284	6	6	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
ALWAYS	322	6	6	100.00
ALWAYS	332	4	4	100.00
ALWAYS	367	6	6	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	499	8	4	50.00
CONT_ASSIGN	568	1	1	100.00
ALWAYS	573	3	3	100.00
ALWAYS	581	12	10	83.33
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
ALWAYS	753	6	6	100.00
CONT_ASSIGN	769	1	1	100.00
ALWAYS	774	6	6	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
ALWAYS	817	3	3	100.00
CONT_ASSIGN	823	1	1	100.00
ALWAYS	845	6	6	100.00
ALWAYS	852	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
129	1	1
130	1	1
131	1	1
143	1	1
144	1	1
146	1	1
148	1	1
150	1	1
151	1	1
153	0	1
			MISSING_ELSE
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	0	1
169	0	1
			==> MISSING_ELSE
174	0	1
175	0	1
176	0	1
			==> MISSING_ELSE
185	1	1
186	1	1
188	1	1
193	1	1
194	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
			MISSING_ELSE
220	1	1
222	1	1
223	1	1
224	1	1
			MISSING_ELSE
227	1	1
228	1	1
230	1	1
232	1	1
233	1	1
235	1	1
237	1	1
238	1	1
240	1	1
241	1	1
243	1	1
244	1	1
246	1	1
247	1	1
249	1	1
250	1	1
253	1	1
255	1	1
256	1	1
262	1	1
266	1	1
267	1	1
269	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
282	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
295	1	1
296	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
307	1	1
308	1	1
311	1	1
312	1	1
317	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
			MISSING_ELSE
332	1	1
333	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
415	1	1
422	1	1
430	1	1
432	1	1
435	1	1
436	1	1
437	1	1
439	1	1
440	1	1
476	1	1
479	1	1
485	1	1
490	1	1
491	1	1
493	1	1
494	1	1
495	1	1
499	1	1
500	1	1
502	1	1
503	0	1
505	0	1
506	0	1
508	0	1
511	1	1
568	1	1
573	1	1
574	1	1
575	1	1
581	1	1
582	1	1
584	1	1
585	1	1
586	0	1
			MISSING_ELSE
588	1	1
589	0	1
			MISSING_ELSE
591	1	1
			MISSING_ELSE
593	1	1
594	1	1
595	1	1
596	1	1
			MISSING_ELSE
601	1	1
602	1	1
609	1	1
610	1	1
720	1	1
748	1	1
749	1	1
750	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
			MISSING_ELSE
761	1	1
769	1	1
774	1	1
775	1	1
777	1	1
781	1	1
785	1	1
789	1	1
811	1	1
815	1	1
817	1	1
818	1	1
820	1	1
823	1	1
845	2	2
846	2	2
847	2	2
			MISSING_ELSE
852	2	2
853	2	2
854	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	131	102	77.86
Logical	131	102	77.86
Non-Logical	0	0
Event	0	0

 LINE       165
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       227
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T8,T15

 LINE       237
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T15

 LINE       237
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T17

 LINE       238
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Not Covered
1	1	Covered	T2,T8,T15

 LINE       238
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T2,T8,T15
1	Covered	T2,T8,T15

 LINE       244
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T15
0	1	Not Covered
1	0	Not Covered

 LINE       250
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T15
0	1	Not Covered
1	0	Not Covered

 LINE       305
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       307
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       308
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       317
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T15,T18
1	1	0	Covered	T2,T8,T15
1	1	1	Covered	T1,T2,T3

 LINE       318
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       319
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       326
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       360
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       415
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       422
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       432
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       479
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T20,T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       495
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       495
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       500
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       503
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       521
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T2,T8,T15
1	1	1	1	Covered	T1,T2,T3

 LINE       595
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Unreachable	T20,T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       720
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       748
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T18

 LINE       748
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       749
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       749
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       750
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       769
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       769
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T8,T15
0	0	1	0	Covered	T2,T8,T15
0	1	0	0	Covered	T8,T15,T18
1	0	0	0	Covered	T8,T15,T18

 LINE       811
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T19,T26,T17	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T6,T27	Yes	T2,T6,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T9,T10,T13	Yes	T9,T10,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T19,T26,T17	Yes	T19,T26,T17	OUTPUT
intr_hmac_err_o	Yes	Yes	T2,T8,T19	Yes	T2,T8,T19	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitHashComplete	169	Not Covered
DoneAwaitHashDone	150	Covered	T1,T2,T3
DoneAwaitMessageComplete	153	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	150	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	153	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	176	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	169	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		85	75	88.24
TERNARY	422	4	4	100.00
TERNARY	432	2	2	100.00
TERNARY	495	2	2	100.00
CASE	146	10	4	40.00
IF	185	2	2	100.00
IF	197	4	4	100.00
IF	222	2	2	100.00
IF	227	5	5	100.00
CASE	271	5	5	100.00
CASE	284	6	6	100.00
IF	322	4	4	100.00
IF	332	3	3	100.00
IF	367	4	4	100.00
IF	435	2	2	100.00
IF	499	4	2	50.00
IF	581	9	7	77.78
IF	754	2	2	100.00
CASE	775	5	5	100.00
IF	817	2	2	100.00
IF	845	4	4	100.00
IF	852	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	422	(fifo_full) ? 
-2-:	422	(fifo_empty_negedge) ? 
-3-:	422	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	432	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	495	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	case (done_state_q)
-2-:	148	if (sha_hash_process)
-3-:	151	if (reg_hash_stop)
-4-:	158	if (reg_hash_done)
-5-:	165	if ((sha_message_length[8:0] == '0))
-6-:	174	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	185	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	if ((!rst_ni))
-2-:	199	if (wipe_secret)
-3-:	201	if ((!cfg_block))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T28,T27,T19
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((digest_size == SHA2_256))
-2-:	228	if ((i < 8))
-3-:	237	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-:	238	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T3
1	0	-	-	Covered	T1,T2,T3
0	-	1	1	Covered	T2,T8,T15
0	-	1	0	Covered	T2,T8,T15
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T2,T8,T15
SHA2_512	Covered	T15,T16,T17
SHA2_None	Covered	T1,T2,T3
default	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	284	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T26,T29,T30
Key_256	Covered	T1,T2,T3
Key_384	Covered	T8,T16,T30
Key_512	Covered	T19,T26,T17
Key_1024	Covered	T17,T31,T32
default	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	322	if ((!rst_ni))
-2-:	324	if (hash_start_or_continue)
-3-:	326	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	if ((!rst_ni))
-2-:	360	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))
-2-:	369	if (hash_start_or_continue)
-3-:	371	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	435	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if (hmac_fifo_wsel)
-2-:	500	if ((digest_size == SHA2_256))
-3-:	503	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	581	if ((!rst_ni))
-2-:	584	if ((!cfg_block))
-3-:	585	if (reg2hw.msg_length_lower.qe)
-4-:	588	if (reg2hw.msg_length_upper.qe)
-5-:	593	if (hash_start)
-6-:	595	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Not Covered
0	1	0	-	-	-	Covered	T1,T2,T3
0	1	-	1	-	-	Not Covered
0	1	-	0	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	754	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T8,T15,T18
update_seckey_inprocess	Covered	T8,T15,T18
hash_start_active	Covered	T2,T8,T15
msg_push_not_allowed	Covered	T2,T8,T15
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	817	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	845	if ((!rst_ni))
-2-:	846	if (reg_hash_process)
-3-:	847	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	852	if ((!rst_ni))
-2-:	853	if (hash_start_or_continue)
-3-:	854	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	344283432	344213468	0	0
FpvSecCmRegWeOnehotCheck_A	344283432	110	0	0
IntrFifoEmptyOKnown	344283432	344213468	0	0
IntrHmacDoneOKnown	344283432	344213468	0	0
TlOAReadyKnown	344283432	344213468	0	0
TlODValidKnown	344283432	344213468	0	0
ValidHashProcessAssert	344283432	35941	0	0
ValidHmacEnConditionAssert	344283432	9300	0	0
ValidWriteAssert	344283432	19803741	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	344283432	19803741	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	344283432	19803741	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	110	0	0
T33	3817	10	0	0
T34	0	20	0	0
T35	0	20	0	0
T36	0	30	0	0
T37	0	30	0	0
T38	355192	0	0	0
T39	137388	0	0	0
T40	4735	0	0	0
T41	397908	0	0	0
T42	127874	0	0	0
T43	500524	0	0	0
T44	136722	0	0	0
T45	16413	0	0	0
T46	2681	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	344213468	0	0
T1	16922	16865	0	0
T2	278464	278372	0	0
T3	87914	87836	0	0
T4	174794	174719	0	0
T5	12192	12142	0	0
T6	850445	850370	0	0
T7	639830	639764	0	0
T8	553065	552986	0	0
T27	131913	131863	0	0
T28	36283	36193	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	35941	0	0
T1	16922	39	0	0
T2	278464	4	0	0
T3	87914	8	0	0
T4	174794	44	0	0
T5	12192	28	0	0
T6	850445	38	0	0
T7	639830	34	0	0
T8	553065	7	0	0
T27	131913	44	0	0
T28	36283	3	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	9300	0	0
T1	16922	18	0	0
T2	278464	15	0	0
T3	87914	2	0	0
T4	174794	22	0	0
T5	12192	16	0	0
T6	850445	19	0	0
T7	639830	22	0	0
T8	553065	13	0	0
T27	131913	25	0	0
T28	36283	2	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	344283432	19803741	0	0
T1	16922	484	0	0
T2	278464	8257	0	0
T3	87914	6938	0	0
T4	174794	31424	0	0
T5	12192	290	0	0
T6	850445	36526	0	0
T7	639830	23508	0	0
T8	553065	17853	0	0
T27	131913	18054	0	0
T28	36283	1925	0	0