Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	371503293	1812433	0	0
intr_enable_rd_A	371503293	2791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371503293	1812433	0	0
T9	395184	136216	0	0
T10	0	36015	0	0
T11	0	82575	0	0
T12	0	31940	0	0
T13	0	105062	0	0
T14	0	272183	0	0
T47	0	172816	0	0
T66	0	7	0	0
T72	0	56608	0	0
T73	0	56227	0	0
T74	1301	0	0	0
T75	5445	0	0	0
T76	1362	0	0	0
T77	394597	0	0	0
T78	10389	0	0	0
T79	1006	0	0	0
T80	1372	0	0	0
T81	72099	0	0	0
T82	390148	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371503293	2791	0	0
T17	396647	23	0	0
T23	1065	0	0	0
T26	279856	31	0	0
T83	0	18	0	0
T84	0	7	0	0
T85	0	85	0	0
T86	0	26	0	0
T87	0	69	0	0
T88	0	8	0	0
T89	0	7	0	0
T90	0	28	0	0
T91	250670	0	0	0
T92	587373	0	0	0
T93	6354	0	0	0
T94	83303	0	0	0
T95	2556	0	0	0
T96	55721	0	0	0
T97	651624	0	0	0