Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	450552687	1899421	0	0
intr_enable_rd_A	450552687	2440	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450552687	1899421	0	0
T5	527019	236972	0	0
T6	2648	0	0	0
T7	159898	0	0	0
T8	0	63325	0	0
T9	0	228477	0	0
T10	0	163756	0	0
T11	0	18367	0	0
T17	79936	0	0	0
T19	685	0	0	0
T21	0	175727	0	0
T22	0	102156	0	0
T24	12377	0	0	0
T25	29000	0	0	0
T26	2631	0	0	0
T55	2886	0	0	0
T56	136356	0	0	0
T65	0	227074	0	0
T66	0	147760	0	0
T67	0	12021	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450552687	2440	0	0
T12	438620	76	0	0
T13	700912	0	0	0
T50	92745	0	0	0
T68	145354	51	0	0
T69	0	12	0	0
T70	0	4	0	0
T71	0	16	0	0
T72	0	83	0	0
T73	0	9	0	0
T74	0	31	0	0
T75	0	13	0	0
T76	0	62	0	0
T77	138689	0	0	0
T78	945	0	0	0
T79	64454	0	0	0
T80	8089	0	0	0
T81	3791	0	0	0
T82	105915	0	0	0