Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.74	94.02	73.91	100.00	40.00	88.51	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	83.30	94.02	77.27	100.00	40.00	88.51	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.30	94.02	77.27	100.00	40.00	88.51	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.46	92.46	85.17	100.00	73.68	85.93	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	89.78	95.33	78.98		100.00	84.81
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	69.73	80.49	53.67		72.00	72.77
u_reg	98.20	94.80	97.48	100.00		98.72	100.00
u_tlul_adapter	88.93	93.95	89.16			79.75	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		184	173	94.02
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	143	15	9	60.00
ALWAYS	184	3	3	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	196	7	7	100.00
ALWAYS	210	3	3	100.00
ALWAYS	221	0	0
ALWAYS	221	21	21	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	270	5	5	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	282	6	6	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	320	6	6	100.00
ALWAYS	330	4	4	100.00
ALWAYS	365	6	6	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
ALWAYS	434	5	5	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
ALWAYS	498	8	5	62.50
CONT_ASSIGN	566	1	1	100.00
ALWAYS	571	3	3	100.00
ALWAYS	579	3	3	100.00
ALWAYS	584	10	8	80.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
ALWAYS	753	6	6	100.00
CONT_ASSIGN	769	1	1	100.00
ALWAYS	774	6	6	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
ALWAYS	817	3	3	100.00
CONT_ASSIGN	823	1	1	100.00
ALWAYS	845	6	6	100.00
ALWAYS	852	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
129	1	1
130	1	1
131	1	1
143	1	1
144	1	1
146	1	1
148	1	1
150	1	1
151	1	1
153	0	1
			MISSING_ELSE
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	0	1
168	0	1
			==> MISSING_ELSE
173	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
198	1	1
199	1	1
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
			MISSING_ELSE
210	2	2
211	1	1
221	1	1
223	1	1
225	1	1
226	1	1
			MISSING_ELSE
229	1	1
231	1	1
232	1	1
234	1	1
236	1	1
237	1	1
239	1	1
241	1	1
242	1	1
244	1	1
245	1	1
247	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
			MISSING_ELSE
261	1	1
265	1	1
266	1	1
268	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
309	1	1
310	1	1
315	1	1
316	1	1
317	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
330	1	1
331	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
			MISSING_ELSE
414	1	1
421	1	1
429	1	1
431	1	1
434	1	1
435	1	1
436	1	1
438	1	1
439	1	1
475	1	1
478	1	1
484	1	1
489	1	1
490	1	1
492	1	1
493	1	1
494	1	1
498	1	1
499	1	1
500	1	1
502	1	1
503	0	1
505	0	1
506	0	1
			==> MISSING_ELSE
509	1	1
566	1	1
571	1	1
572	1	1
573	1	1
579	2	2
580	1	1
584	1	1
585	1	1
586	1	1
587	0	1
			MISSING_ELSE
589	1	1
590	0	1
			MISSING_ELSE
			MISSING_ELSE
594	1	1
595	1	1
596	1	1
597	1	1
			MISSING_ELSE
601	1	1
602	1	1
609	1	1
610	1	1
720	1	1
748	1	1
749	1	1
750	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
			MISSING_ELSE
761	1	1
769	1	1
774	1	1
775	1	1
777	1	1
781	1	1
785	1	1
789	1	1
811	1	1
815	1	1
817	1	1
818	1	1
820	1	1
823	1	1
845	2	2
846	2	2
847	2	2
			MISSING_ELSE
852	2	2
853	2	2
854	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	138	102	73.91
Logical	138	102	73.91
Non-Logical	0	0
Event	0	0

 LINE       165
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       241
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T15,T16

 LINE       241
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T15,T16

 LINE       241
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       242
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T12
1	0	Not Covered
1	1	Covered	T5,T15,T12

 LINE       242
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T5,T15,T12
1	Covered	T5,T15,T12

 LINE       248
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T15,T12
0	1	Not Covered
1	0	Not Covered

 LINE       254
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T15,T12
0	1	Not Covered
1	0	Not Covered

 LINE       303
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       304
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       305
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       306
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       315
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T15
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T1,T3,T4

 LINE       316
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       317
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       324
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       358
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       414
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       421
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       421
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       421
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T3,T4
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T3,T4

 LINE       429
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T17
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T5,T7,T17
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       478
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T7,T17,T18
1	1	1	Covered	T1,T3,T4

 LINE       494
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       494
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       500
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       503
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       519
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       566
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       596
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Unreachable	T7,T17,T18
1	1	1	Covered	T1,T3,T4

 LINE       616
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       616
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       720
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T20

 LINE       748
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T15

 LINE       748
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       749
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       749
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       750
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       769
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       769
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T4,T5,T6
1	0	0	0	Covered	T4,T5,T15

 LINE       811
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T7	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T5,T15,T12	Yes	T5,T15,T12	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitHashComplete	168	Not Covered
DoneAwaitHashDone	150	Covered	T1,T3,T4
DoneAwaitMessageComplete	153	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	150	Covered	T1,T3,T4
DoneAwaitCmd->DoneAwaitMessageComplete	153	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	175	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	160	Covered	T1,T3,T4
DoneAwaitMessageComplete->DoneAwaitHashComplete	168	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		87	77	88.51
TERNARY	421	4	4	100.00
TERNARY	431	2	2	100.00
TERNARY	494	2	2	100.00
CASE	146	10	4	40.00
IF	184	2	2	100.00
IF	197	3	3	100.00
IF	210	2	2	100.00
IF	223	2	2	100.00
IF	231	5	5	100.00
CASE	270	5	5	100.00
CASE	282	6	6	100.00
IF	320	4	4	100.00
IF	330	3	3	100.00
IF	365	4	4	100.00
IF	434	2	2	100.00
IF	498	4	2	50.00
IF	579	2	2	100.00
IF	585	5	3	60.00
IF	594	3	3	100.00
IF	754	2	2	100.00
CASE	775	5	5	100.00
IF	817	2	2	100.00
IF	845	4	4	100.00
IF	852	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	421	(fifo_full) ? 
-2-:	421	(fifo_empty_negedge) ? 
-3-:	421	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T17

	LineNo.	Expression
-1-:	494	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	case (done_state_q)
-2-:	148	if (sha_hash_process)
-3-:	151	if (reg_hash_stop)
-4-:	158	if (reg_hash_done)
-5-:	165	if ((sha_message_length[8:0] == '0))
-6-:	173	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T3,T4
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T3,T4
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T3,T4
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	if (wipe_secret)
-2-:	199	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	210	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((digest_size == SHA2_256))
-2-:	232	if ((i < 8))
-3-:	241	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-:	242	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T3,T4
1	0	-	-	Covered	T1,T3,T4
0	-	1	1	Covered	T5,T15,T12
0	-	1	0	Covered	T5,T15,T12
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	270	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T5,T15,T16
SHA2_512	Covered	T12,T13,T14
SHA2_None	Covered	T1,T2,T3
default	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	282	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T5,T13,T16
Key_256	Covered	T1,T2,T3
Key_384	Covered	T5,T15,T23
Key_512	Covered	T4,T5,T7
Key_1024	Covered	T4,T12,T14
default	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	322	if (hash_start_or_continue)
-3-:	324	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if ((!rst_ni))
-2-:	358	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))
-2-:	367	if (hash_start_or_continue)
-3-:	369	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if (hmac_fifo_wsel)
-2-:	500	if ((digest_size == SHA2_256))
-3-:	503	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T4,T5
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	579	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if ((!cfg_block))
-2-:	586	if (reg2hw.msg_length_lower.qe)
-3-:	589	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	594	if (hash_start)
-2-:	596	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	754	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T4,T5,T15
update_seckey_inprocess	Covered	T4,T5,T6
hash_start_active	Covered	T3,T4,T5
msg_push_not_allowed	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	817	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	845	if ((!rst_ni))
-2-:	846	if (reg_hash_process)
-3-:	847	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	852	if ((!rst_ni))
-2-:	853	if (hash_start_or_continue)
-3-:	854	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	438639053	438565771	0	0
FpvSecCmRegWeOnehotCheck_A	438639053	120	0	0
IntrFifoEmptyOKnown	438639053	438565771	0	0
IntrHmacDoneOKnown	438639053	438565771	0	0
TlOAReadyKnown	438639053	438565771	0	0
TlODValidKnown	438639053	438565771	0	0
ValidHashProcessAssert	438639053	45571	0	0
ValidHmacEnConditionAssert	438639053	10527	0	0
ValidWriteAssert	438639053	25198016	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	438639053	25198016	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	120	0	0
T27	15302	30	0	0
T28	0	10	0	0
T29	0	30	0	0
T30	0	20	0	0
T31	0	30	0	0
T32	1151	0	0	0
T33	2743	0	0	0
T34	21556	0	0	0
T35	6853	0	0	0
T36	503146	0	0	0
T37	422115	0	0	0
T38	257958	0	0	0
T39	1175	0	0	0
T40	22621	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	45571	0	0
T1	153541	15	0	0
T2	1103	0	0	0
T3	221990	1	0	0
T4	439880	280	0	0
T5	527019	745	0	0
T6	2648	4	0	0
T7	159898	395	0	0
T17	0	27	0	0
T24	12377	31	0	0
T25	29000	5	0	0
T26	2631	4	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	10527	0	0
T1	153541	8	0	0
T2	1103	0	0	0
T3	221990	3	0	0
T4	439880	61	0	0
T5	527019	134	0	0
T6	2648	1	0	0
T7	159898	74	0	0
T17	0	15	0	0
T24	12377	12	0	0
T25	29000	5	0	0
T26	2631	1	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		184	173	94.02
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	143	15	9	60.00
ALWAYS	184	3	3	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	196	7	7	100.00
ALWAYS	210	3	3	100.00
ALWAYS	221	0	0
ALWAYS	221	21	21	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	270	5	5	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	282	6	6	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	320	6	6	100.00
ALWAYS	330	4	4	100.00
ALWAYS	365	6	6	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
ALWAYS	434	5	5	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
ALWAYS	498	8	5	62.50
CONT_ASSIGN	566	1	1	100.00
ALWAYS	571	3	3	100.00
ALWAYS	579	3	3	100.00
ALWAYS	584	10	8	80.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
ALWAYS	753	6	6	100.00
CONT_ASSIGN	769	1	1	100.00
ALWAYS	774	6	6	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
ALWAYS	817	3	3	100.00
CONT_ASSIGN	823	1	1	100.00
ALWAYS	845	6	6	100.00
ALWAYS	852	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
129	1	1
130	1	1
131	1	1
143	1	1
144	1	1
146	1	1
148	1	1
150	1	1
151	1	1
153	0	1
			MISSING_ELSE
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	0	1
168	0	1
			==> MISSING_ELSE
173	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
198	1	1
199	1	1
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
			MISSING_ELSE
210	2	2
211	1	1
221	1	1
223	1	1
225	1	1
226	1	1
			MISSING_ELSE
229	1	1
231	1	1
232	1	1
234	1	1
236	1	1
237	1	1
239	1	1
241	1	1
242	1	1
244	1	1
245	1	1
247	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
			MISSING_ELSE
261	1	1
265	1	1
266	1	1
268	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
309	1	1
310	1	1
315	1	1
316	1	1
317	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
330	1	1
331	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
			MISSING_ELSE
414	1	1
421	1	1
429	1	1
431	1	1
434	1	1
435	1	1
436	1	1
438	1	1
439	1	1
475	1	1
478	1	1
484	1	1
489	1	1
490	1	1
492	1	1
493	1	1
494	1	1
498	1	1
499	1	1
500	1	1
502	1	1
503	0	1
505	0	1
506	0	1
			==> MISSING_ELSE
509	1	1
566	1	1
571	1	1
572	1	1
573	1	1
579	2	2
580	1	1
584	1	1
585	1	1
586	1	1
587	0	1
			MISSING_ELSE
589	1	1
590	0	1
			MISSING_ELSE
			MISSING_ELSE
594	1	1
595	1	1
596	1	1
597	1	1
			MISSING_ELSE
601	1	1
602	1	1
609	1	1
610	1	1
720	1	1
748	1	1
749	1	1
750	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
			MISSING_ELSE
761	1	1
769	1	1
774	1	1
775	1	1
777	1	1
781	1	1
785	1	1
789	1	1
811	1	1
815	1	1
817	1	1
818	1	1
820	1	1
823	1	1
845	2	2
846	2	2
847	2	2
			MISSING_ELSE
852	2	2
853	2	2
854	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	132	102	77.27
Logical	132	102	77.27
Non-Logical	0	0
Event	0	0

 LINE       165
 EXPRESSION (sha_message_length[8:0] == '0)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       241
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T15,T16

 LINE       241
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T15,T16

 LINE       241
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       242
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T12
1	0	Not Covered
1	1	Covered	T5,T15,T12

 LINE       242
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T5,T15,T12
1	Covered	T5,T15,T12

 LINE       248
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T15,T12
0	1	Not Covered
1	0	Not Covered

 LINE       254
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T15,T12
0	1	Not Covered
1	0	Not Covered

 LINE       303
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       304
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       305
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       306
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       315
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
             -------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T15
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T1,T3,T4

 LINE       316
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
             --------1--------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       317
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       324
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       358
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       414
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       421
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       421
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       421
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T3,T4
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T3,T4

 LINE       429
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T17
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T5,T7,T17
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Excluded		VC_COV_UNR

 LINE       478
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T7,T17,T18
1	1	1	Covered	T1,T3,T4

 LINE       494
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       494
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       500
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       503
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       503
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       519
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       566
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T3,T4

 LINE       596
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Unreachable	T7,T17,T18
1	1	1	Covered	T1,T3,T4

 LINE       616
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       616
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       720
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T20

 LINE       748
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T15

 LINE       748
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       749
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       749
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       750
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       769
 EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
             ----------------1----------------   -----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       769
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Covered	T4,T5,T6
1	0	0	0	Covered	T4,T5,T15

 LINE       811
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T4,T5
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T7	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T5,T15,T12	Yes	T5,T15,T12	OUTPUT
intr_hmac_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	160	Covered	T1,T2,T3
DoneAwaitHashComplete	168	Not Covered
DoneAwaitHashDone	150	Covered	T1,T3,T4
DoneAwaitMessageComplete	153	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	150	Covered	T1,T3,T4
DoneAwaitCmd->DoneAwaitMessageComplete	153	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	175	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	160	Covered	T1,T3,T4
DoneAwaitMessageComplete->DoneAwaitHashComplete	168	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		87	77	88.51
TERNARY	421	4	4	100.00
TERNARY	431	2	2	100.00
TERNARY	494	2	2	100.00
CASE	146	10	4	40.00
IF	184	2	2	100.00
IF	197	3	3	100.00
IF	210	2	2	100.00
IF	223	2	2	100.00
IF	231	5	5	100.00
CASE	270	5	5	100.00
CASE	282	6	6	100.00
IF	320	4	4	100.00
IF	330	3	3	100.00
IF	365	4	4	100.00
IF	434	2	2	100.00
IF	498	4	2	50.00
IF	579	2	2	100.00
IF	585	5	3	60.00
IF	594	3	3	100.00
IF	754	2	2	100.00
CASE	775	5	5	100.00
IF	817	2	2	100.00
IF	845	4	4	100.00
IF	852	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	421	(fifo_full) ? 
-2-:	421	(fifo_empty_negedge) ? 
-3-:	421	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T17

	LineNo.	Expression
-1-:	494	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	case (done_state_q)
-2-:	148	if (sha_hash_process)
-3-:	151	if (reg_hash_stop)
-4-:	158	if (reg_hash_done)
-5-:	165	if ((sha_message_length[8:0] == '0))
-6-:	173	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T3,T4
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T3,T4
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T3,T4
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	if (wipe_secret)
-2-:	199	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	210	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((digest_size == SHA2_256))
-2-:	232	if ((i < 8))
-3-:	241	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-:	242	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T3,T4
1	0	-	-	Covered	T1,T3,T4
0	-	1	1	Covered	T5,T15,T12
0	-	1	0	Covered	T5,T15,T12
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	270	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T5,T15,T16
SHA2_512	Covered	T12,T13,T14
SHA2_None	Covered	T1,T2,T3
default	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	282	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T5,T13,T16
Key_256	Covered	T1,T2,T3
Key_384	Covered	T5,T15,T23
Key_512	Covered	T4,T5,T7
Key_1024	Covered	T4,T12,T14
default	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	322	if (hash_start_or_continue)
-3-:	324	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if ((!rst_ni))
-2-:	358	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))
-2-:	367	if (hash_start_or_continue)
-3-:	369	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if (hmac_fifo_wsel)
-2-:	500	if ((digest_size == SHA2_256))
-3-:	503	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T4,T5
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	579	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	585	if ((!cfg_block))
-2-:	586	if (reg2hw.msg_length_lower.qe)
-3-:	589	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	594	if (hash_start)
-2-:	596	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	754	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T4,T5,T15
update_seckey_inprocess	Covered	T4,T5,T6
hash_start_active	Covered	T3,T4,T5
msg_push_not_allowed	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	817	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	845	if ((!rst_ni))
-2-:	846	if (reg_hash_process)
-3-:	847	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	852	if ((!rst_ni))
-2-:	853	if (hash_start_or_continue)
-3-:	854	if (reg_hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	438639053	438565771	0	0
FpvSecCmRegWeOnehotCheck_A	438639053	120	0	0
IntrFifoEmptyOKnown	438639053	438565771	0	0
IntrHmacDoneOKnown	438639053	438565771	0	0
TlOAReadyKnown	438639053	438565771	0	0
TlODValidKnown	438639053	438565771	0	0
ValidHashProcessAssert	438639053	45571	0	0
ValidHmacEnConditionAssert	438639053	10527	0	0
ValidWriteAssert	438639053	25198016	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	438639053	25198016	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	438639053	25198016	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	120	0	0
T27	15302	30	0	0
T28	0	10	0	0
T29	0	30	0	0
T30	0	20	0	0
T31	0	30	0	0
T32	1151	0	0	0
T33	2743	0	0	0
T34	21556	0	0	0
T35	6853	0	0	0
T36	503146	0	0	0
T37	422115	0	0	0
T38	257958	0	0	0
T39	1175	0	0	0
T40	22621	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	438565771	0	0
T1	153541	153491	0	0
T2	1103	1024	0	0
T3	221990	221932	0	0
T4	439880	439863	0	0
T5	527019	527010	0	0
T6	2648	2562	0	0
T7	159898	159850	0	0
T24	12377	12293	0	0
T25	29000	28929	0	0
T26	2631	2558	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	45571	0	0
T1	153541	15	0	0
T2	1103	0	0	0
T3	221990	1	0	0
T4	439880	280	0	0
T5	527019	745	0	0
T6	2648	4	0	0
T7	159898	395	0	0
T17	0	27	0	0
T24	12377	31	0	0
T25	29000	5	0	0
T26	2631	4	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	10527	0	0
T1	153541	8	0	0
T2	1103	0	0	0
T3	221990	3	0	0
T4	439880	61	0	0
T5	527019	134	0	0
T6	2648	1	0	0
T7	159898	74	0	0
T17	0	15	0	0
T24	12377	12	0	0
T25	29000	5	0	0
T26	2631	1	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	438639053	25198016	0	0
T1	153541	6143	0	0
T2	1103	0	0	0
T3	221990	7405	0	0
T4	439880	151178	0	0
T5	527019	305202	0	0
T6	2648	42	0	0
T7	159898	309688	0	0
T17	0	45046	0	0
T24	12377	336	0	0
T25	29000	3311	0	0
T26	2631	51	0	0