Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.78	95.33	78.98		100.00	84.81

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	89.78	95.33	78.98		100.00	84.81

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.78	95.33	78.98		100.00	84.81

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.78	95.33	78.98		100.00	84.81

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		150	143	95.33
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
ALWAYS	134	21	21	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
ALWAYS	213	16	15	93.75
CONT_ASSIGN	237	1	1	100.00
ALWAYS	240	4	4	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	256	10	6	60.00
ALWAYS	274	3	3	100.00
ALWAYS	280	6	6	100.00
ALWAYS	290	4	4	100.00
ALWAYS	298	6	6	100.00
CONT_ASSIGN	307	1	1	100.00
ALWAYS	310	3	3	100.00
ALWAYS	315	64	62	96.88
CONT_ASSIGN	444	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
126	1	1
127	1	1
129	1	1
130	1	1
134	1	1
136	1	1
138	1	1
140	1	1
142	1	1
146	1	1
148	1	1
150	1	1
152	1	1
156	1	1
158	1	1
160	1	1
162	1	1
166	1	1
167	1	1
169	1	1
170	1	1
175	1	1
176	1	1
178	1	1
179	1	1
194	1	1
196	1	1
197	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
			MISSING_ELSE
234	0	1
237	1	1
240	1	1
241	1	1
242	1	1
243	1	1
248	1	1
256	1	1
257	1	1
258	1	1
259	1	1
262	0	1
263	0	1
264	0	1
265	0	1
268	1	1
269	1	1
			MISSING_ELSE
274	2	2
275	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
290	1	1
291	1	1
292	1	1
293	1	1
			MISSING_ELSE
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
			==> MISSING_ELSE
307	1	1
310	2	2
311	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
331	1	1
332	1	1
334	1	1
335	1	1
336	1	1
337	1	1
339	1	1
344	1	1
346	1	1
347	1	1
349	1	1
351	1	1
353	1	1
358	1	1
359	1	1
361	1	1
362	0	1
363	0	1
			MISSING_ELSE
366	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
378	1	1
380	1	1
381	1	1
382	1	1
384	1	1
387	1	1
392	1	1
393	1	1
394	1	1
395	1	1
397	1	1
401	1	1
403	1	1
404	1	1
405	1	1
406	1	1
408	1	1
414	1	1
415	1	1
417	1	1
418	1	1
420	1	1
422	1	1
424	1	1
430	1	1
432	1	1
444	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	176	139	78.98
Logical	176	139	78.98
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       126
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       126
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       127
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       194
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       194
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       194
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       196
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       197
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       197
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       197
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T22,T41
1	0	Not Covered
1	1	Not Covered

 LINE       197
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       197
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T13,T22,T41
1	0	Covered	T42,T43,T44

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T42,T43,T44

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T22,T41

 LINE       197
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       197
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       197
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T22,T41
1	0	Not Covered
1	1	Not Covered

 LINE       197
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       197
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T13,T22,T41
1	0	Covered	T42,T43,T44

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T42,T43,T44

 LINE       197
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T22,T41

 LINE       197
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       197
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       218
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T4

 LINE       219
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T3,T4

 LINE       221
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T16
0	1	Covered	T41,T45,T46
1	0	Covered	T47,T48,T46

 LINE       221
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T47,T48,T46

 LINE       221
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T41,T45,T46

 LINE       224
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       226
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T1,T4,T5

 LINE       228
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T42,T43,T44

 LINE       230
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T15
1	Covered	T13,T22,T49

 LINE       241
 EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       242
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T15,T16
1	Not Covered

 LINE       243
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Not Covered

 LINE       248
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       284
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T4,T5

 LINE       302
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       307
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       307
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       359
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       361
 EXPRESSION ((round_q == Inner) && reg_hash_continue_i)
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       361
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       366
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       366
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       366
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       366
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       366
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       370
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       381
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       397
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       397
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T5
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T4,T5

 LINE       397
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       397
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       397
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T4,T5

 LINE       397
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       397
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       397
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       397
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       397
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       397
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       444
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start_i || reg_hash_continue_i) ))
             --------1-------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       444
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       444
 SUB-EXPRESSION ( ! (reg_hash_start_i || reg_hash_continue_i) )
                    --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       444
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	382	Covered	T1,T4,T5
StIPad	332	Covered	T1,T4,T5
StIdle	339	Covered	T1,T2,T3
StMsg	347	Covered	T1,T4,T5
StOPad	401	Covered	T1,T4,T5
StPushToMsgFifo	384	Covered	T1,T4,T5
StWaitResp	368	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
StDone->StIdle	430	Covered	T1,T4,T5
StIPad->StMsg	347	Covered	T1,T4,T5
StIdle->StIPad	332	Covered	T1,T4,T5
StMsg->StWaitResp	368	Covered	T1,T4,T5
StOPad->StMsg	418	Covered	T1,T4,T5
StPushToMsgFifo->StOPad	401	Covered	T1,T4,T5
StWaitResp->StDone	382	Covered	T1,T4,T5
StWaitResp->StPushToMsgFifo	384	Covered	T1,T4,T5

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		79	67	84.81
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	127	2	2	100.00
TERNARY	194	2	2	100.00
TERNARY	196	2	2	100.00
TERNARY	197	7	4	57.14
TERNARY	307	2	2	100.00
CASE	134	6	5	83.33
IF	214	9	8	88.89
CASE	240	4	4	100.00
IF	257	7	3	42.86
IF	274	2	2	100.00
IF	280	4	4	100.00
IF	290	3	3	100.00
IF	298	4	3	75.00
IF	310	2	2	100.00
CASE	329	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	123	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	127	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	((!hmac_en_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	197	((!hmac_en_i)) ? 
-2-:	197	(((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? 
-3-:	197	(((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-4-:	197	(((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? 
-5-:	197	(((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-6-:	197	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T4,T5
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T4,T5
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	307	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	134	case (key_length_i)

Branches:

-1-	Status	Tests
Key_128	Covered	T5,T13,T16
Key_256	Covered	T1,T2,T3
Key_384	Covered	T5,T15,T23
Key_512	Covered	T4,T5,T7
Key_1024	Covered	T4,T12,T14
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!hmac_en_i))
-2-:	218	if ((sel_msglen == SelIPadMsg))
-3-:	219	if ((digest_size_i == SHA2_256))
-4-:	221	if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
-5-:	224	if ((sel_msglen == SelOPadMsg))
-6-:	226	if ((digest_size_i == SHA2_256))
-7-:	228	if ((digest_size_i == SHA2_384))
-8-:	230	if ((digest_size_i == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T3,T4
0	1	0	1	-	-	-	-	Covered	T41,T47,T48
0	1	0	0	-	-	-	-	Covered	T3,T4,T16
0	0	-	-	1	1	-	-	Covered	T1,T4,T5
0	0	-	-	1	0	1	-	Covered	T42,T43,T44
0	0	-	-	1	0	0	1	Covered	T13,T22,T49
0	0	-	-	1	0	0	0	Covered	T4,T5,T15
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	240	case (digest_size_i)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T5,T15,T16
SHA2_512	Covered	T12,T13,T14
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	if (clr_txcount)
-2-:	259	if (load_txcount)
-3-:	262	case (digest_size_i)
-4-:	268	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T4,T5
0	1	SHA2_256	-	Not Covered
0	1	SHA2_384	-	Not Covered
0	1	SHA2_512	-	Not Covered
0	1	default	-	Not Covered
0	0	-	1	Covered	T1,T3,T4
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	280	if ((!rst_ni))
-2-:	282	if (reg_hash_process_i)
-3-:	284	if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	292	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	298	if ((!rst_ni))
-2-:	300	if (clr_fifo_wdata_sel)
-3-:	302	if ((fifo_wsel_o && fifo_wvalid_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	0	0	Not Covered

	LineNo.	Expression
-1-:	310	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	case (st_q)
-2-:	331	if ((hmac_en_i && reg_hash_start_i))
-3-:	346	if (txcnt_eq_blksz)
-4-:	361	if (((round_q == Inner) && reg_hash_continue_i))
-5-:	366	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o)))
-6-:	380	if (sha_hash_done_i)
-7-:	381	if ((round_q == Outer))
-8-:	397	if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))))
-9-:	417	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StIPad	-	0	-	-	-	-	-	-	Covered	T1,T4,T5
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
StMsg	-	-	-	1	-	-	-	-	Covered	T1,T4,T5
StMsg	-	-	-	0	-	-	-	-	Covered	T1,T4,T5
StWaitResp	-	-	-	-	1	1	-	-	Covered	T1,T4,T5
StWaitResp	-	-	-	-	1	0	-	-	Covered	T1,T4,T5
StWaitResp	-	-	-	-	0	-	-	-	Covered	T1,T4,T5
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T1,T4,T5
StOPad	-	-	-	-	-	-	-	1	Covered	T1,T4,T5
StOPad	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
StDone	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	Not Covered