Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39800346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42657614

1

T1

228042

T2

191861

T3

34261

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32814867	1			T1	180123		T2	150217		T3	2859
values[0x0]	23128010	1			T1	120040		T2	106604		T3	17943
values[0x1]	26515083	1			T1	132001		T2	119051		T3	19195

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29270357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53187603

1

T1

278360

T2

237382

T3

36472

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300203	1			T1	1834		T2	1454		T17	251
valid_sources[0x01]	270178	1			T1	1618		T2	1442		T17	268
valid_sources[0x02]	279766	1			T1	1794		T2	1530		T17	253
valid_sources[0x03]	270977	1			T1	1892		T2	1472		T17	214
valid_sources[0x04]	314405	1			T1	1720		T2	1434		T17	277
valid_sources[0x05]	279501	1			T1	1516		T2	1498		T17	265
valid_sources[0x06]	281292	1			T1	1577		T2	1460		T3	2122
valid_sources[0x07]	280690	1			T1	1407		T2	1460		T17	274
valid_sources[0x08]	278926	1			T1	1588		T2	1512		T17	280
valid_sources[0x09]	274794	1			T1	1928		T2	1450		T17	241
valid_sources[0x0a]	279413	1			T1	1738		T2	1444		T17	194
valid_sources[0x0b]	281657	1			T1	1813		T2	1497		T17	225
valid_sources[0x0c]	1034769	1			T1	1622		T2	1418		T17	284
valid_sources[0x0d]	300815	1			T1	1723		T2	1398		T17	259
valid_sources[0x0e]	270521	1			T1	1746		T2	1517		T17	206
valid_sources[0x0f]	271676	1			T1	1636		T2	1436		T17	260
valid_sources[0x10]	279398	1			T1	1771		T2	1470		T17	222
valid_sources[0x11]	276471	1			T1	1605		T2	1428		T17	218
valid_sources[0x12]	285468	1			T1	1662		T2	1498		T17	216
valid_sources[0x13]	299694	1			T1	1637		T2	1444		T17	279
valid_sources[0x14]	287051	1			T1	2022		T2	1519		T17	225
valid_sources[0x15]	298640	1			T1	1612		T2	1478		T3	290
valid_sources[0x16]	326625	1			T1	1646		T2	1411		T17	249
valid_sources[0x17]	285619	1			T1	1740		T2	1497		T17	210
valid_sources[0x18]	289441	1			T1	1787		T2	1489		T17	247
valid_sources[0x19]	644593	1			T1	1722		T2	1449		T3	1685
valid_sources[0x1a]	280502	1			T1	1660		T2	1486		T17	283
valid_sources[0x1b]	278196	1			T1	1800		T2	1469		T17	225
valid_sources[0x1c]	279813	1			T1	1685		T2	1506		T17	236
valid_sources[0x1d]	269283	1			T1	1722		T2	1456		T3	273
valid_sources[0x1e]	276845	1			T1	1652		T2	1437		T3	461
valid_sources[0x1f]	274585	1			T1	1509		T2	1494		T17	228
valid_sources[0x20]	269317	1			T1	1597		T2	1428		T17	242
valid_sources[0x21]	293467	1			T1	1679		T2	1462		T17	256
valid_sources[0x22]	282658	1			T1	1748		T2	1499		T17	192
valid_sources[0x23]	275185	1			T1	1539		T2	1435		T17	222
valid_sources[0x24]	269528	1			T1	1725		T2	1452		T17	224
valid_sources[0x25]	290205	1			T1	1594		T2	1516		T17	219
valid_sources[0x26]	268830	1			T1	1579		T2	1513		T17	224
valid_sources[0x27]	289292	1			T1	1658		T2	1455		T17	273
valid_sources[0x28]	297316	1			T1	1829		T2	1482		T17	235
valid_sources[0x29]	291894	1			T1	1778		T2	1493		T3	3420
valid_sources[0x2a]	291806	1			T1	1536		T2	1492		T17	251
valid_sources[0x2b]	271559	1			T1	1643		T2	1415		T17	236
valid_sources[0x2c]	280529	1			T1	1803		T2	1512		T17	213
valid_sources[0x2d]	265988	1			T1	1745		T2	1500		T17	230
valid_sources[0x2e]	299942	1			T1	1722		T2	1431		T17	223
valid_sources[0x2f]	280738	1			T1	1587		T2	1465		T17	249
valid_sources[0x30]	276162	1			T1	1730		T2	1409		T17	244
valid_sources[0x31]	286829	1			T1	1766		T2	1531		T17	237
valid_sources[0x32]	278268	1			T1	1724		T2	1507		T17	261
valid_sources[0x33]	301657	1			T1	1464		T2	1484		T17	201
valid_sources[0x34]	294877	1			T1	1594		T2	1491		T17	234
valid_sources[0x35]	271274	1			T1	1998		T2	1494		T17	263
valid_sources[0x36]	298042	1			T1	1838		T2	1508		T17	217
valid_sources[0x37]	267746	1			T1	1671		T2	1492		T3	237
valid_sources[0x38]	273184	1			T1	1436		T2	1433		T3	391
valid_sources[0x39]	658485	1			T1	1448		T2	1467		T3	642
valid_sources[0x3a]	267890	1			T1	1753		T2	1461		T17	232
valid_sources[0x3b]	274466	1			T1	1561		T2	1478		T17	290
valid_sources[0x3c]	267710	1			T1	1646		T2	1467		T17	246
valid_sources[0x3d]	273085	1			T1	1713		T2	1418		T17	227
valid_sources[0x3e]	289626	1			T1	1739		T2	1430		T17	240
valid_sources[0x3f]	291147	1			T1	1556		T2	1488		T3	342
valid_sources[0x40]	332803	1			T1	1786		T2	1401		T17	258
valid_sources[0x41]	297973	1			T1	1798		T2	1470		T17	239
valid_sources[0x42]	273168	1			T1	1704		T2	1457		T17	245
valid_sources[0x43]	304649	1			T1	1537		T2	1487		T3	1829
valid_sources[0x44]	274006	1			T1	1824		T2	1445		T17	235
valid_sources[0x45]	674824	1			T1	1736		T2	1557		T17	231
valid_sources[0x46]	281518	1			T1	1633		T2	1469		T3	161
valid_sources[0x47]	659041	1			T1	1781		T2	1466		T17	232
valid_sources[0x48]	642795	1			T1	1626		T2	1520		T17	236
valid_sources[0x49]	985077	1			T1	1564		T2	1555		T17	207
valid_sources[0x4a]	275537	1			T1	1696		T2	1496		T17	213
valid_sources[0x4b]	270517	1			T1	1685		T2	1462		T17	223
valid_sources[0x4c]	303448	1			T1	1568		T2	1480		T17	260
valid_sources[0x4d]	294200	1			T1	1763		T2	1506		T17	231
valid_sources[0x4e]	281323	1			T1	1763		T2	1486		T17	219
valid_sources[0x4f]	279714	1			T1	1541		T2	1472		T17	229
valid_sources[0x50]	294756	1			T1	1703		T2	1435		T17	246
valid_sources[0x51]	661782	1			T1	1713		T2	1506		T3	1192
valid_sources[0x52]	279509	1			T1	1660		T2	1445		T17	228
valid_sources[0x53]	619808	1			T1	1499		T2	1482		T17	255
valid_sources[0x54]	276972	1			T1	1892		T2	1413		T17	270
valid_sources[0x55]	274420	1			T1	1674		T2	1443		T17	235
valid_sources[0x56]	294767	1			T1	1839		T2	1471		T17	219
valid_sources[0x57]	273647	1			T1	1903		T2	1434		T3	1084
valid_sources[0x58]	288675	1			T1	1634		T2	1505		T17	228
valid_sources[0x59]	281660	1			T1	1726		T2	1523		T17	255
valid_sources[0x5a]	603396	1			T1	1726		T2	1418		T17	219
valid_sources[0x5b]	305448	1			T1	1882		T2	1501		T17	207
valid_sources[0x5c]	276421	1			T1	1844		T2	1436		T17	231
valid_sources[0x5d]	276792	1			T1	1696		T2	1492		T3	259
valid_sources[0x5e]	285222	1			T1	1766		T2	1503		T17	266
valid_sources[0x5f]	283369	1			T1	1758		T2	1553		T17	255
valid_sources[0x60]	276434	1			T1	1852		T2	1459		T17	255
valid_sources[0x61]	289845	1			T1	1635		T2	1574		T17	212
valid_sources[0x62]	294387	1			T1	1679		T2	1473		T17	247
valid_sources[0x63]	281284	1			T1	1710		T2	1466		T17	234
valid_sources[0x64]	266983	1			T1	1500		T2	1460		T17	283
valid_sources[0x65]	279201	1			T1	1661		T2	1495		T17	240
valid_sources[0x66]	279592	1			T1	1705		T2	1502		T17	243
valid_sources[0x67]	277712	1			T1	1594		T2	1421		T17	239
valid_sources[0x68]	273660	1			T1	1720		T2	1429		T17	215
valid_sources[0x69]	269784	1			T1	1693		T2	1485		T17	267
valid_sources[0x6a]	969008	1			T1	1725		T2	1492		T3	4361
valid_sources[0x6b]	281820	1			T1	1536		T2	1425		T17	221
valid_sources[0x6c]	280233	1			T1	1897		T2	1473		T17	272
valid_sources[0x6d]	266951	1			T1	1757		T2	1441		T17	261
valid_sources[0x6e]	359917	1			T1	1774		T2	1400		T17	244
valid_sources[0x6f]	278626	1			T1	1732		T2	1459		T3	8295
valid_sources[0x70]	302090	1			T1	1689		T2	1500		T17	200
valid_sources[0x71]	279338	1			T1	1737		T2	1375		T3	231
valid_sources[0x72]	266048	1			T1	1448		T2	1471		T17	259
valid_sources[0x73]	317235	1			T1	1698		T2	1456		T17	228
valid_sources[0x74]	632398	1			T1	1891		T2	1494		T3	333
valid_sources[0x75]	275149	1			T1	1733		T2	1520		T17	253
valid_sources[0x76]	283303	1			T1	1769		T2	1419		T17	272
valid_sources[0x77]	279232	1			T1	1642		T2	1422		T17	213
valid_sources[0x78]	282289	1			T1	1859		T2	1398		T17	296
valid_sources[0x79]	608113	1			T1	1756		T2	1529		T17	250
valid_sources[0x7a]	275138	1			T1	1737		T2	1454		T17	291
valid_sources[0x7b]	276327	1			T1	1541		T2	1486		T17	250
valid_sources[0x7c]	297777	1			T1	1815		T2	1442		T17	243
valid_sources[0x7d]	275077	1			T1	1754		T2	1502		T17	272
valid_sources[0x7e]	1067049	1			T1	1499		T2	1402		T17	248
valid_sources[0x7f]	272134	1			T1	1522		T2	1515		T17	235
valid_sources[0x80]	272748	1			T1	1631		T2	1404		T17	249

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15852465

1

T1

90212

T2

75196

T3

841

values[0x0]

all_enables

biggest_size

14098415

1

T1

72637

T2

62048

T3

16729

values[0x1]

all_enables

biggest_size

12706734

1

T1

65193

T2

54617

T3

16691