Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44358710

1

T1

204122

T2

184011

T3

5736

full_word

42954886

1

T1

228042

T2

191861

T3

34261

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87313146	1			T1	432164		T2	375872		T3	39997
auto[TlIntgErrCmd]	144	1			T59	12		T60	10		T61	9
auto[TlIntgErrData]	159	1			T59	11		T60	4		T61	15
auto[TlIntgErrBoth]	147	1			T59	7		T60	6		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34349557

1

T1

180123

T2

150217

T3

2859

auto[1]

52964039

1

T1

252041

T2

225655

T3

37138

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18379589	1			T1	89911		T2	75021		T3	2018
auto[TlIntgErrNone]	partial	auto[1]	25978704	1			T1	114211		T2	108990		T3	3718
auto[TlIntgErrNone]	full_word	auto[0]	15969775	1			T1	90212		T2	75196		T3	841
auto[TlIntgErrNone]	full_word	auto[1]	26985078	1			T1	137830		T2	116665		T3	33420
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T59	7		T60	5		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T59	4		T60	4		T61	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T61	2		T113	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T59	1		T60	1		T61	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T59	6		T60	1		T61	7
auto[TlIntgErrData]	partial	auto[1]	77	1			T59	3		T60	3		T61	7
auto[TlIntgErrData]	full_word	auto[0]	2	1			T59	1		T117	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T59	1		T61	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T59	4		T60	1		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T59	3		T60	3		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T60	1		T61	2		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T60	1		T114	1		T119	1