Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	470344131	2607115	0	0
intr_enable_rd_A	470344131	2605	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344131	2607115	0	0
T4	190769	84775	0	0
T5	0	207886	0	0
T6	0	187301	0	0
T7	0	99064	0	0
T9	0	34209	0	0
T20	0	287874	0	0
T23	1128	0	0	0
T49	0	35510	0	0
T56	130903	0	0	0
T64	0	197635	0	0
T65	0	256101	0	0
T66	0	47516	0	0
T67	158935	0	0	0
T68	470084	0	0	0
T69	10059	0	0	0
T70	248434	0	0	0
T71	15598	0	0	0
T72	783864	0	0	0
T73	188839	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344131	2605	0	0
T31	940591	63	0	0
T50	0	16	0	0
T60	0	144	0	0
T74	0	33	0	0
T75	0	35	0	0
T76	0	13	0	0
T77	0	19	0	0
T78	0	4	0	0
T79	0	30	0	0
T80	0	11	0	0
T81	1026	0	0	0
T82	12418	0	0	0
T83	41446	0	0	0
T84	116561	0	0	0
T85	757885	0	0	0
T86	3346	0	0	0
T87	1389	0	0	0
T88	194713	0	0	0
T89	142860	0	0	0