Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33867544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36099107

1

T1

8

T2

17907

T3

152

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27984328	1			T1	1		T2	4904		T3	141
values[0x0]	19565353	1			T1	9		T2	8116		T3	59
values[0x1]	22416970	1			T1	8		T2	8568		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24964030	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45002621

1

T1

10

T2

19180

T3

179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	244421	1			T2	50		T4	96		T5	1589
valid_sources[0x01]	306399	1			T2	33		T4	57		T5	1649
valid_sources[0x02]	247751	1			T2	69		T4	47		T5	1575
valid_sources[0x03]	276074	1			T2	171		T4	52		T5	1584
valid_sources[0x04]	296006	1			T2	62		T4	124		T5	1627
valid_sources[0x05]	239873	1			T2	55		T4	73		T5	1579
valid_sources[0x06]	274987	1			T2	27		T4	99		T5	1473
valid_sources[0x07]	251730	1			T2	26		T4	152		T5	1665
valid_sources[0x08]	234416	1			T2	177		T4	36		T5	1465
valid_sources[0x09]	242935	1			T2	120		T4	136		T5	1718
valid_sources[0x0a]	238828	1			T2	72		T4	50		T5	1653
valid_sources[0x0b]	256379	1			T2	47		T4	86		T5	1682
valid_sources[0x0c]	233494	1			T2	27		T4	51		T5	1537
valid_sources[0x0d]	268564	1			T2	60		T4	96		T5	1625
valid_sources[0x0e]	282475	1			T2	59		T4	114		T5	1704
valid_sources[0x0f]	668414	1			T2	159		T4	145		T5	1499
valid_sources[0x10]	243389	1			T2	71		T4	60		T5	1691
valid_sources[0x11]	228578	1			T1	1		T2	37		T4	80
valid_sources[0x12]	241799	1			T2	44		T4	61		T5	1607
valid_sources[0x13]	260204	1			T2	258		T4	78		T5	1689
valid_sources[0x14]	236711	1			T2	77		T4	61		T5	1589
valid_sources[0x15]	255204	1			T2	180		T4	52		T5	1559
valid_sources[0x16]	244733	1			T2	1286		T4	112		T5	1615
valid_sources[0x17]	261442	1			T2	56		T4	147		T5	1557
valid_sources[0x18]	231527	1			T2	55		T4	74		T5	1587
valid_sources[0x19]	225563	1			T2	74		T4	37		T5	1618
valid_sources[0x1a]	246515	1			T2	60		T4	46		T5	1558
valid_sources[0x1b]	232458	1			T2	59		T4	88		T5	1631
valid_sources[0x1c]	542537	1			T2	74		T4	151		T5	1574
valid_sources[0x1d]	228677	1			T2	53		T4	50		T5	1538
valid_sources[0x1e]	238701	1			T2	98		T4	75		T5	1709
valid_sources[0x1f]	255628	1			T2	96		T4	164		T5	1697
valid_sources[0x20]	225338	1			T2	47		T4	108		T5	1598
valid_sources[0x21]	256188	1			T2	51		T4	11		T5	1754
valid_sources[0x22]	252541	1			T2	54		T4	56		T5	1546
valid_sources[0x23]	227309	1			T2	157		T4	28		T5	1497
valid_sources[0x24]	234962	1			T2	79		T4	171		T5	1641
valid_sources[0x25]	236446	1			T2	29		T4	70		T5	1560
valid_sources[0x26]	230950	1			T1	2		T2	66		T4	26
valid_sources[0x27]	233266	1			T2	30		T4	78		T5	1595
valid_sources[0x28]	255699	1			T2	103		T4	56		T5	1648
valid_sources[0x29]	268457	1			T1	1		T2	77		T4	25
valid_sources[0x2a]	234565	1			T1	1		T2	238		T4	141
valid_sources[0x2b]	231481	1			T2	89		T4	97		T5	1593
valid_sources[0x2c]	243847	1			T2	56		T4	98		T5	1751
valid_sources[0x2d]	238222	1			T2	62		T4	15		T5	1617
valid_sources[0x2e]	245138	1			T2	46		T4	60		T5	1728
valid_sources[0x2f]	240401	1			T2	82		T4	33		T5	1442
valid_sources[0x30]	228126	1			T2	315		T4	126		T5	1562
valid_sources[0x31]	239142	1			T2	71		T4	43		T5	1671
valid_sources[0x32]	238263	1			T2	66		T4	185		T5	1654
valid_sources[0x33]	226569	1			T2	85		T4	35		T5	1593
valid_sources[0x34]	271775	1			T2	94		T4	65		T5	1803
valid_sources[0x35]	229160	1			T2	190		T4	152		T5	1491
valid_sources[0x36]	231252	1			T2	34		T4	11		T5	1632
valid_sources[0x37]	234086	1			T2	1042		T4	48		T5	1508
valid_sources[0x38]	254604	1			T2	41		T4	119		T5	1612
valid_sources[0x39]	230690	1			T2	65		T4	59		T5	1683
valid_sources[0x3a]	257997	1			T2	84		T4	33		T5	1662
valid_sources[0x3b]	245301	1			T2	41		T4	51		T5	1676
valid_sources[0x3c]	234916	1			T2	79		T4	97		T5	1513
valid_sources[0x3d]	264645	1			T2	64		T4	13		T5	1558
valid_sources[0x3e]	233454	1			T2	60		T4	148		T5	1651
valid_sources[0x3f]	251874	1			T2	71		T4	147		T5	1647
valid_sources[0x40]	230256	1			T2	83		T4	57		T5	1667
valid_sources[0x41]	256803	1			T2	44		T4	78		T5	1606
valid_sources[0x42]	229670	1			T2	79		T4	61		T5	1590
valid_sources[0x43]	229430	1			T2	60		T4	50		T5	1630
valid_sources[0x44]	235737	1			T2	56		T4	169		T5	1700
valid_sources[0x45]	250311	1			T2	51		T4	71		T5	1643
valid_sources[0x46]	685534	1			T2	60		T4	128		T5	1578
valid_sources[0x47]	256659	1			T2	50		T4	24		T5	1587
valid_sources[0x48]	275338	1			T2	86		T4	2		T5	1735
valid_sources[0x49]	240838	1			T2	61		T4	82		T5	1657
valid_sources[0x4a]	245138	1			T2	143		T4	522		T5	1607
valid_sources[0x4b]	250252	1			T2	152		T4	33		T5	1719
valid_sources[0x4c]	251369	1			T2	65		T4	169		T5	1587
valid_sources[0x4d]	239221	1			T2	90		T4	71		T5	1624
valid_sources[0x4e]	245590	1			T2	33		T4	109		T5	1540
valid_sources[0x4f]	266614	1			T2	250		T4	2203		T5	1619
valid_sources[0x50]	264241	1			T2	56		T4	23		T5	1589
valid_sources[0x51]	236456	1			T2	44		T4	41		T5	1612
valid_sources[0x52]	254465	1			T2	92		T4	122		T5	1645
valid_sources[0x53]	322732	1			T2	67		T4	62		T5	1600
valid_sources[0x54]	236543	1			T2	69		T4	43		T5	1617
valid_sources[0x55]	245092	1			T2	73		T4	82		T5	1904
valid_sources[0x56]	227804	1			T2	62		T4	96		T5	1653
valid_sources[0x57]	229382	1			T2	52		T4	85		T5	1629
valid_sources[0x58]	234034	1			T2	66		T4	80		T5	1694
valid_sources[0x59]	618374	1			T2	76		T4	108		T5	1519
valid_sources[0x5a]	675530	1			T2	21		T4	119		T5	1504
valid_sources[0x5b]	249349	1			T2	75		T4	69		T5	1615
valid_sources[0x5c]	256801	1			T2	35		T4	134		T5	1603
valid_sources[0x5d]	226201	1			T2	172		T4	79		T5	1598
valid_sources[0x5e]	276270	1			T2	125		T4	1		T5	1609
valid_sources[0x5f]	243604	1			T1	1		T2	44		T4	40
valid_sources[0x60]	249787	1			T2	34		T4	141		T5	1569
valid_sources[0x61]	235980	1			T2	52		T4	71		T5	1584
valid_sources[0x62]	263149	1			T2	58		T4	82		T5	1660
valid_sources[0x63]	630142	1			T2	42		T4	126		T5	1447
valid_sources[0x64]	252798	1			T2	61		T4	45		T5	1588
valid_sources[0x65]	256779	1			T2	47		T4	43		T5	1550
valid_sources[0x66]	260491	1			T2	74		T4	82		T5	1671
valid_sources[0x67]	258259	1			T1	1		T2	112		T4	197
valid_sources[0x68]	241746	1			T2	59		T4	50		T5	1578
valid_sources[0x69]	243458	1			T2	62		T4	38		T5	1668
valid_sources[0x6a]	236074	1			T2	124		T4	61		T5	1660
valid_sources[0x6b]	225762	1			T2	68		T4	90		T5	1626
valid_sources[0x6c]	229240	1			T2	65		T4	154		T5	1640
valid_sources[0x6d]	248766	1			T2	75		T5	1650		T18	6
valid_sources[0x6e]	246425	1			T2	115		T4	26		T5	1552
valid_sources[0x6f]	244689	1			T2	69		T4	44		T5	1605
valid_sources[0x70]	239735	1			T2	48		T4	39		T5	1682
valid_sources[0x71]	620222	1			T2	84		T4	23		T5	1667
valid_sources[0x72]	250399	1			T1	3		T2	45		T4	79
valid_sources[0x73]	229624	1			T2	62		T4	66		T5	1607
valid_sources[0x74]	237376	1			T2	64		T4	33		T5	1586
valid_sources[0x75]	235048	1			T2	49		T4	88		T5	1639
valid_sources[0x76]	257472	1			T2	106		T4	53		T5	1679
valid_sources[0x77]	229952	1			T2	45		T4	324		T5	1638
valid_sources[0x78]	535056	1			T2	63		T4	89		T5	1570
valid_sources[0x79]	245270	1			T2	19		T4	34		T5	1766
valid_sources[0x7a]	238791	1			T2	33		T4	53		T5	1603
valid_sources[0x7b]	230473	1			T2	32		T4	60		T5	1511
valid_sources[0x7c]	233208	1			T2	36		T4	63		T5	1494
valid_sources[0x7d]	265377	1			T2	61		T4	41		T5	1630
valid_sources[0x7e]	246336	1			T2	84		T4	136		T5	1543
valid_sources[0x7f]	241250	1			T2	106		T4	47		T5	1631
valid_sources[0x80]	248016	1			T2	32		T4	126		T5	1539

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13547706

1

T2

1644

T3

81

T4

9027

values[0x0]

all_enables

biggest_size

11869217

1

T1

7

T2

7935

T3

33

values[0x1]

all_enables

biggest_size

10682184

1

T1

1

T2

8328

T3

38