Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

37047635

1

T1

10

T2

3681

T3

122

full_word

36305771

1

T1

8

T2

17907

T3

152

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	73353046	1			T1	18		T2	21588		T3	274
auto[TlIntgErrCmd]	122	1			T58	9		T59	4		T60	9
auto[TlIntgErrData]	117	1			T58	6		T59	6		T60	7
auto[TlIntgErrBoth]	121	1			T58	5		T59	10		T60	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29047784

1

T1

1

T2

4904

T3

141

auto[1]

44305622

1

T1

17

T2

16684

T3

133

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15419064	1			T1	1		T2	3260		T3	60
auto[TlIntgErrNone]	partial	auto[1]	21628247	1			T1	9		T2	421		T3	62
auto[TlIntgErrNone]	full_word	auto[0]	13628559	1			T2	1644		T3	81		T4	9027
auto[TlIntgErrNone]	full_word	auto[1]	22677176	1			T1	8		T2	16263		T3	71
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T58	2		T60	1		T108	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T58	6		T59	4		T60	6
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T60	1		T110	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T58	1		T60	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T58	2		T59	2		T60	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T58	4		T59	4		T60	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T109	1		T111	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T108	1		T107	1		T63	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T58	1		T59	6		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T58	3		T59	4		T60	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T58	1		T110	1		T107	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T104	2		T63	2		T113	1