Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	372934175	1829806	0	0
intr_enable_rd_A	372934175	1464	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372934175	1829806	0	0
T7	425294	180405	0	0
T8	0	102810	0	0
T9	0	41207	0	0
T10	0	90455	0	0
T11	0	407870	0	0
T16	954139	0	0	0
T19	109619	0	0	0
T26	98065	0	0	0
T33	287664	0	0	0
T34	352989	0	0	0
T44	148365	0	0	0
T49	0	56287	0	0
T55	2412	0	0	0
T56	177016	0	0	0
T57	12949	0	0	0
T64	0	85073	0	0
T65	0	45065	0	0
T66	0	105027	0	0
T67	0	54081	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372934175	1464	0	0
T29	726550	25	0	0
T46	0	24	0	0
T68	0	6	0	0
T69	0	23	0	0
T70	0	6	0	0
T71	0	12	0	0
T72	0	35	0	0
T73	0	31	0	0
T74	0	6	0	0
T75	0	9	0	0
T76	441239	0	0	0
T77	353661	0	0	0
T78	305420	0	0	0
T79	75451	0	0	0
T80	126297	0	0	0
T81	683589	0	0	0
T82	27711	0	0	0
T83	713363	0	0	0
T84	58244	0	0	0