Module Definition
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Module : prim_sha2
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.17 91.95 63.57 90.00 87.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode 83.17 91.95 63.57 90.00 87.18



Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.17 91.95 63.57 90.00 87.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.32 88.85 55.93 76.00 76.51


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
54.20 58.00 45.07 59.52 u_prim_sha2_512


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_pad 66.04 85.00 47.69 66.67 64.79


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sha2
Line No.TotalCoveredPercent
TOTAL14913791.95
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
ALWAYS88141285.71
ALWAYS11344100.00
ALWAYS11911981.82
ALWAYS13833100.00
ALWAYS144282278.57
ALWAYS18533100.00
CONT_ASSIGN19011100.00
ALWAYS28677100.00
ALWAYS30333100.00
CONT_ASSIGN30811100.00
ALWAYS31333100.00
CONT_ASSIGN31811100.00
ALWAYS32133100.00
ALWAYS33433100.00
ALWAYS3392626100.00
ALWAYS39033100.00
ALWAYS40433100.00
ALWAYS41133100.00
CONT_ASSIGN41511100.00
ALWAYS418232191.30
CONT_ASSIGN46511100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1
76 1 1
88 1 1
89 1 1
90 1 1
91 1 1
92 1 1
93 1 1
96 1 1
97 1 1
98 1 1
100 1 1
102 0 1
103 0 1
==> MISSING_ELSE
105 1 1
107 1 1
MISSING_ELSE
113 2 2
114 2 2
==> MISSING_ELSE
119 1 1
120 1 1
121 1 1
122 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
130 0 1
131 0 1
==> MISSING_ELSE
MISSING_ELSE
138 2 2
139 1 1
144 1 1
145 1 1
146 1 1
147 1 1
149 1 1
150 1 1
151 1 1
152 1 1
153 0 1
154 0 1
155 0 1
156 0 1
==> MISSING_ELSE
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
165 1 1
166 1 1
167 1 1
168 2 2
==> MISSING_ELSE
170 1 1
172 0 1
173 0 1
174 1 1
176 1 1
177 1 1
MISSING_ELSE
MISSING_ELSE
185 2 2
186 1 1
190 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
294 1 1
296 1 1
MISSING_ELSE
303 2 2
304 1 1
308 1 1
313 2 2
314 1 1
318 1 1
321 2 2
322 1 1
334 2 2
335 1 1
339 1 1
340 1 1
341 1 1
343 1 1
345 2 2
346 1 1
350 1 1
352 1 1
353 1 1
354 1 1
355 1 1
357 1 1
359 1 1
360 1 1
365 1 1
366 1 1
368 1 1
369 1 1
370 1 1
372 1 1
381 1 1
382 1 1
383 1 1
384 1 1
385 1 1
MISSING_ELSE
390 2 2
391 1 1
404 2 2
405 1 1
411 2 2
412 1 1
415 1 1
418 1 1
419 1 1
420 1 1
421 1 1
422 1 1
424 1 1
426 1 1
427 1 1
428 1 1
430 1 1
435 1 1
436 1 1
439 1 1
440 1 1
441 1 1
443 1 1
448 1 1
449 1 1
450 0 1
451 0 1
453 1 1
462 2 2
MISSING_ELSE
465 1 1
491 1 1
494 1 1


Cond Coverage for Module : prim_sha2
TotalCoveredPercent
Conditions1408963.57
Logical1408963.57
Non-Logical00
Event00

 LINE       74
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T3,T4

 LINE       76
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       76
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       91
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       98
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       127
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       130
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       130
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       168
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       170
 EXPRESSION ((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_384))
             ----------1----------    ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11Not Covered

 LINE       170
 SUB-EXPRESSION (hash_done_o == 1'b1)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       170
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       174
 EXPRESSION ((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_256))
             ----------1----------    ----------------2---------------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT2,T3,T4

 LINE       174
 SUB-EXPRESSION (hash_done_o == 1'b1)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       174
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       287
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       308
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       308
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       308
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       354
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       365
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       415
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T16,T13
10CoveredT2,T3,T4

 LINE       415
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT7,T16,T13

 LINE       426
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       436
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10CoveredT2,T3,T4

 LINE       436
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       436
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-Not Covered
1-CoveredT2,T3,T4

 LINE       436
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       436
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       436
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       436
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       436
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       449
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       462
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       465
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       465
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       465
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT2,T3,T4

 LINE       465
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       465
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       465
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       465
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       465
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       465
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       465
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       465
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       491
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT2,T3,T4

 LINE       494
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       494
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       494
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : prim_sha2
Summary for FSM :: fifo_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: fifo_st_q
statesLine No.CoveredTests
FifoIdle 339 Covered T1,T2,T3
FifoLoadFromFifo 345 Covered T2,T3,T4
FifoWait 355 Covered T2,T3,T4


transitionsLine No.CoveredTests
FifoIdle->FifoLoadFromFifo 345 Covered T2,T3,T4
FifoLoadFromFifo->FifoIdle 339 Covered T10,T8,T9
FifoLoadFromFifo->FifoWait 355 Covered T2,T3,T4
FifoWait->FifoIdle 339 Covered T2,T3,T4
FifoWait->FifoLoadFromFifo 370 Covered T2,T3,T4


Summary for FSM :: sha_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 4 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: sha_st_q
statesLine No.CoveredTests
ShaCompress 428 Covered T2,T3,T4
ShaIdle 430 Covered T1,T2,T3
ShaUpdateDigest 441 Covered T2,T3,T4


transitionsLine No.CoveredTests
ShaCompress->ShaIdle 462 Covered T7,T10,T8
ShaCompress->ShaUpdateDigest 441 Covered T2,T3,T4
ShaIdle->ShaCompress 428 Covered T2,T3,T4
ShaUpdateDigest->ShaCompress 451 Not Covered
ShaUpdateDigest->ShaIdle 453 Covered T2,T3,T4



Branch Coverage for Module : prim_sha2
Line No.TotalCoveredPercent
Branches 78 68 87.18
TERNARY 76 3 3 100.00
TERNARY 308 3 3 100.00
TERNARY 465 3 2 66.67
IF 287 4 4 100.00
IF 303 2 2 100.00
IF 313 2 2 100.00
IF 321 2 2 100.00
IF 334 2 2 100.00
CASE 343 9 8 88.89
IF 381 3 3 100.00
IF 390 2 2 100.00
IF 404 2 2 100.00
IF 411 2 2 100.00
CASE 424 8 6 75.00
IF 462 2 2 100.00
IF 89 8 6 75.00
IF 113 3 2 66.67
IF 120 6 4 66.67
IF 138 2 2 100.00
IF 145 8 7 87.50
IF 185 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 (hash_go) ? -2-: 76 (hash_done_o) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 308 (((~sha_en_i) || hash_go)) ? -2-: 308 (update_w_from_fifo) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 465 ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? -2-: 465 ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 287 if (((!sha_en_i) || hash_go)) -2-: 289 if (run_hash) -3-: 290 if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T2,T3,T4
0 1 0 Covered T2,T3,T4
0 0 - Covered T2,T3,T4


LineNo. Expression -1-: 303 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 313 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 321 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 case (fifo_st_q) -2-: 345 if (hash_go) -3-: 350 if ((!shaf_rvalid)) -4-: 354 if ((w_index_q == 4'd15)) -5-: 365 if ((msg_feed_complete && one_chunk_done)) -6-: 369 if (one_chunk_done)

Branches:
-1--2--3--4--5--6-StatusTests
FifoIdle 1 - - - - Covered T2,T3,T4
FifoIdle 0 - - - - Covered T1,T2,T3
FifoLoadFromFifo - 1 - - - Covered T2,T3,T4
FifoLoadFromFifo - 0 1 - - Covered T2,T3,T4
FifoLoadFromFifo - 0 0 - - Covered T2,T3,T4
FifoWait - - - 1 - Covered T2,T3,T4
FifoWait - - - 0 1 Covered T2,T3,T4
FifoWait - - - 0 0 Covered T2,T3,T4
default - - - - - Not Covered


LineNo. Expression -1-: 381 if ((!sha_en_i)) -2-: 384 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 404 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 411 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 case (sha_st_q) -2-: 426 if ((fifo_st_q == FifoWait)) -3-: 436 if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))) -4-: 440 if (one_chunk_done) -5-: 449 if ((fifo_st_q == FifoWait))

Branches:
-1--2--3--4--5-StatusTests
ShaIdle 1 - - - Covered T2,T3,T4
ShaIdle 0 - - - Covered T1,T2,T3
ShaCompress - 1 - - Covered T2,T3,T4
ShaCompress - 0 1 - Covered T2,T3,T4
ShaCompress - 0 0 - Covered T2,T3,T4
ShaUpdateDigest - - - 1 Not Covered
ShaUpdateDigest - - - 0 Covered T2,T3,T4
default - - - - Not Covered


LineNo. Expression -1-: 462 if (((!sha_en_i) || hash_go))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 89 if (wipe_secret_i) -2-: 91 if (((!sha_en_i) || hash_go)) -3-: 93 if (((!run_hash) && update_w_from_fifo)) -4-: 97 if (calculate_next_w) -5-: 98 if ((digest_mode_flag_q == SHA2_256)) -6-: 102 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -7-: 105 if (run_hash)

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T7,T26,T27
0 1 - - - - - Covered T1,T2,T3
0 0 1 - - - - Covered T2,T3,T4
0 0 0 1 1 - - Covered T2,T3,T4
0 0 0 1 0 1 - Not Covered
0 0 0 1 0 0 - Not Covered
0 0 0 0 - - 1 Covered T2,T3,T4
0 0 0 0 - - 0 Covered T2,T3,T4


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 114 if (MultimodeEn)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 120 if (wipe_secret_i) -2-: 124 if (init_hash) -3-: 126 if (run_hash) -4-: 127 if ((digest_mode_flag_q == SHA2_256)) -5-: 130 if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T26,T27
0 1 - - - Covered T2,T3,T4
0 0 1 1 - Covered T2,T3,T4
0 0 1 0 1 Not Covered
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 138 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 145 if (wipe_secret_i) -2-: 149 if (hash_start_i) -3-: 159 if (clear_digest) -4-: 161 if ((!sha_en_i)) -5-: 165 if (update_digest) -6-: 170 if (((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_384))) -7-: 174 if (((hash_done_o == 1'b1) && (digest_mode_flag_q == SHA2_256)))

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T7,T26,T27
0 1 - - - - - Covered T2,T3,T4
0 0 1 - - - - Covered T7,T16,T13
0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 1 1 - Not Covered
0 0 0 0 1 0 1 Covered T2,T3,T4
0 0 0 0 1 0 0 Covered T2,T3,T4
0 0 0 0 0 - - Covered T2,T3,T4


LineNo. Expression -1-: 185 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%