Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	399674905	2636362	0	0
intr_enable_rd_A	399674905	4497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399674905	2636362	0	0
T4	848063	35900	0	0
T5	181849	0	0	0
T6	135069	0	0	0
T7	0	310741	0	0
T8	0	52891	0	0
T9	0	100876	0	0
T10	0	55484	0	0
T11	0	49051	0	0
T18	289075	0	0	0
T19	201321	0	0	0
T20	33496	0	0	0
T23	1192	0	0	0
T30	57185	0	0	0
T42	212837	0	0	0
T43	2650	0	0	0
T63	0	120272	0	0
T64	0	25545	0	0
T65	0	147505	0	0
T66	0	148857	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399674905	4497	0	0
T14	455893	64	0	0
T26	584459	0	0	0
T40	41636	0	0	0
T41	783116	0	0	0
T44	0	74	0	0
T46	344752	0	0	0
T47	0	83	0	0
T52	101597	0	0	0
T56	0	81	0	0
T67	0	10	0	0
T68	0	37	0	0
T69	0	46	0	0
T70	0	22	0	0
T71	0	16	0	0
T72	0	25	0	0
T73	87298	0	0	0
T74	20365	0	0	0
T75	314680	0	0	0
T76	31167	0	0	0