Line Coverage for Module :
hmac
| Line No. | Total | Covered | Percent |
TOTAL | | 184 | 173 | 94.02 |
CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
ALWAYS | 143 | 15 | 9 | 60.00 |
ALWAYS | 184 | 3 | 3 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
ALWAYS | 196 | 7 | 7 | 100.00 |
ALWAYS | 210 | 3 | 3 | 100.00 |
ALWAYS | 221 | 0 | 0 | |
ALWAYS | 221 | 21 | 21 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
ALWAYS | 270 | 5 | 5 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
ALWAYS | 282 | 6 | 6 | 100.00 |
CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 306 | 1 | 1 | 100.00 |
CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
ALWAYS | 320 | 6 | 6 | 100.00 |
ALWAYS | 330 | 4 | 4 | 100.00 |
ALWAYS | 365 | 6 | 6 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
ALWAYS | 434 | 5 | 5 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
CONT_ASSIGN | 484 | 1 | 1 | 100.00 |
CONT_ASSIGN | 489 | 1 | 1 | 100.00 |
CONT_ASSIGN | 490 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 493 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
ALWAYS | 498 | 8 | 5 | 62.50 |
CONT_ASSIGN | 567 | 1 | 1 | 100.00 |
ALWAYS | 572 | 3 | 3 | 100.00 |
ALWAYS | 580 | 3 | 3 | 100.00 |
ALWAYS | 585 | 10 | 8 | 80.00 |
CONT_ASSIGN | 602 | 1 | 1 | 100.00 |
CONT_ASSIGN | 603 | 1 | 1 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 611 | 1 | 1 | 100.00 |
CONT_ASSIGN | 719 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 748 | 1 | 1 | 100.00 |
CONT_ASSIGN | 749 | 1 | 1 | 100.00 |
ALWAYS | 752 | 6 | 6 | 100.00 |
CONT_ASSIGN | 768 | 1 | 1 | 100.00 |
ALWAYS | 773 | 6 | 6 | 100.00 |
CONT_ASSIGN | 810 | 1 | 1 | 100.00 |
CONT_ASSIGN | 814 | 1 | 1 | 100.00 |
ALWAYS | 816 | 3 | 3 | 100.00 |
CONT_ASSIGN | 822 | 1 | 1 | 100.00 |
ALWAYS | 844 | 6 | 6 | 100.00 |
ALWAYS | 851 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
146 |
1 |
1 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
0 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
|
|
|
MISSING_ELSE |
165 |
0 |
1 |
168 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
173 |
0 |
1 |
174 |
0 |
1 |
175 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
210 |
2 |
2 |
211 |
1 |
1 |
221 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
239 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
|
|
|
MISSING_ELSE |
261 |
1 |
1 |
265 |
1 |
1 |
266 |
1 |
1 |
268 |
1 |
1 |
270 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
280 |
1 |
1 |
282 |
1 |
1 |
283 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
287 |
1 |
1 |
293 |
1 |
1 |
294 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
303 |
1 |
1 |
304 |
1 |
1 |
305 |
1 |
1 |
306 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
330 |
1 |
1 |
331 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
|
|
|
MISSING_ELSE |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
|
|
|
MISSING_ELSE |
414 |
1 |
1 |
421 |
1 |
1 |
429 |
1 |
1 |
431 |
1 |
1 |
434 |
1 |
1 |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
475 |
1 |
1 |
478 |
1 |
1 |
484 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
492 |
1 |
1 |
493 |
1 |
1 |
494 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
500 |
1 |
1 |
502 |
1 |
1 |
503 |
0 |
1 |
505 |
0 |
1 |
506 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
509 |
1 |
1 |
567 |
1 |
1 |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
580 |
2 |
2 |
581 |
1 |
1 |
585 |
1 |
1 |
586 |
1 |
1 |
587 |
1 |
1 |
588 |
0 |
1 |
|
|
|
MISSING_ELSE |
590 |
1 |
1 |
591 |
0 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
595 |
1 |
1 |
596 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
610 |
1 |
1 |
611 |
1 |
1 |
719 |
1 |
1 |
747 |
1 |
1 |
748 |
1 |
1 |
749 |
1 |
1 |
752 |
1 |
1 |
753 |
1 |
1 |
754 |
1 |
1 |
755 |
1 |
1 |
756 |
1 |
1 |
|
|
|
MISSING_ELSE |
760 |
1 |
1 |
768 |
1 |
1 |
773 |
1 |
1 |
774 |
1 |
1 |
776 |
1 |
1 |
780 |
1 |
1 |
784 |
1 |
1 |
788 |
1 |
1 |
810 |
1 |
1 |
814 |
1 |
1 |
816 |
1 |
1 |
817 |
1 |
1 |
819 |
1 |
1 |
822 |
1 |
1 |
844 |
2 |
2 |
845 |
2 |
2 |
846 |
2 |
2 |
|
|
|
MISSING_ELSE |
851 |
2 |
2 |
852 |
2 |
2 |
853 |
2 |
2 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
hmac
| Total | Covered | Percent |
Conditions | 138 | 102 | 73.91 |
Logical | 138 | 102 | 73.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 165
EXPRESSION (sha_message_length[8:0] == '0)
---------------1---------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 231
EXPRESSION (digest_size == SHA2_256)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 241
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T14,T15 |
1 | 0 | Covered | T1,T16,T17 |
LINE 241
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T16,T17 |
LINE 241
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T14,T15 |
LINE 242
EXPRESSION (((i % 2) == 0) && (i < 15))
-------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T14 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T14 |
LINE 242
SUB-EXPRESSION ((i % 2) == 0)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T4,T14 |
1 | Covered | T1,T4,T14 |
LINE 248
EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
---------1--------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T14 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 254
EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
---------1--------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T14 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 303
EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
------------1----------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 304
EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
-----------1----------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Not Covered | |
LINE 305
EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
-------------1------------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Not Covered | |
LINE 306
EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
-------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 315
EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
-------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T4,T11 |
1 | 1 | 0 | Covered | T1,T4,T11 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 316
EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
--------1-------- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 317
EXPRESSION (hash_start | hash_continue)
-----1---- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 324
EXPRESSION (reg_hash_done || reg_hash_stop)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 358
EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
-------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 414
EXPRESSION (fifo_empty_q & ((~fifo_empty)))
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 421
EXPRESSION
Number Term
1 fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 421
SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 421
SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 421
SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
-------1------ --------2-------- --------3------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Covered | T1,T3,T4 |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 429
EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T19 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 431
EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
-------1-------
-1- | Status | Tests |
0 | Covered | T4,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 475
EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
------1----- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Not Covered | |
LINE 478
EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
------1----- ---------2--------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | T6,T19,T20 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 494
EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 494
SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
-------1------ -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 500
EXPRESSION (digest_size == SHA2_256)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T3,T4 |
LINE 503
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 503
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 503
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 519
EXPRESSION (fifo_wvalid & sha_en)
-----1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 567
EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
------1----- -----2----- ---------3--------- -----4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Covered | T1,T4,T11 |
1 | 1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 597
EXPRESSION (msg_write && sha_en && packer_ready)
----1---- ---2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | T6,T19,T20 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 617
EXPRESSION (msg_write & sha_en)
----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 617
EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
-----1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 719
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T21,T22 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T23,T21 |
LINE 747
EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
------------------1----------------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 747
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 748
EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
------------------1----------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 748
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 749
EXPRESSION (msg_fifo_req & ((~msg_allowed)))
------1----- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 768
EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
----------------1---------------- -----------------------------------------------2----------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T18 |
LINE 768
SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
-----------1----------- -----------2----------- --------3-------- ----------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T1,T4,T11 |
0 | 0 | 1 | 0 | Covered | T1,T4,T11 |
0 | 1 | 0 | 0 | Covered | T1,T4,T18 |
1 | 0 | 0 | 0 | Covered | T1,T4,T11 |
LINE 810
EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
----------1--------- --------2------- -------3------ ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
Toggle Coverage for Module :
hmac
| Total | Covered | Percent |
Totals |
30 |
30 |
100.00 |
Total Bits |
346 |
346 |
100.00 |
Total Bits 0->1 |
173 |
173 |
100.00 |
Total Bits 1->0 |
173 |
173 |
100.00 |
| | | |
Ports |
30 |
30 |
100.00 |
Port Bits |
346 |
346 |
100.00 |
Port Bits 0->1 |
173 |
173 |
100.00 |
Port Bits 1->0 |
173 |
173 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T19,T24 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T18,T20 |
Yes |
T4,T18,T20 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T4,T11,T7 |
Yes |
T4,T11,T7 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T23,T24 |
Yes |
T2,T23,T24 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T23,T24 |
Yes |
T2,T23,T24 |
OUTPUT |
intr_hmac_done_o |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
intr_fifo_empty_o |
Yes |
Yes |
T4,T25,T11 |
Yes |
T4,T25,T11 |
OUTPUT |
intr_hmac_err_o |
Yes |
Yes |
T1,T4,T18 |
Yes |
T1,T4,T18 |
OUTPUT |
idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
OUTPUT |
*Tests covering at least one bit in the range
FSM Coverage for Module :
hmac
Summary for FSM :: done_state_q
| Total | Covered | Percent | |
States |
4 |
2 |
50.00 |
(Not included in score) |
Transitions |
5 |
2 |
40.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: done_state_q
states | Line No. | Covered | Tests |
DoneAwaitCmd |
160 |
Covered |
T1,T2,T3 |
DoneAwaitHashComplete |
168 |
Not Covered |
|
DoneAwaitHashDone |
150 |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete |
153 |
Not Covered |
|
transitions | Line No. | Covered | Tests |
DoneAwaitCmd->DoneAwaitHashDone |
150 |
Covered |
T1,T3,T4 |
DoneAwaitCmd->DoneAwaitMessageComplete |
153 |
Not Covered |
|
DoneAwaitHashComplete->DoneAwaitCmd |
175 |
Not Covered |
|
DoneAwaitHashDone->DoneAwaitCmd |
160 |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete->DoneAwaitHashComplete |
168 |
Not Covered |
|
Branch Coverage for Module :
hmac
| Line No. | Total | Covered | Percent |
Branches |
|
87 |
77 |
88.51 |
TERNARY |
421 |
4 |
4 |
100.00 |
TERNARY |
431 |
2 |
2 |
100.00 |
TERNARY |
494 |
2 |
2 |
100.00 |
CASE |
146 |
10 |
4 |
40.00 |
IF |
184 |
2 |
2 |
100.00 |
IF |
197 |
3 |
3 |
100.00 |
IF |
210 |
2 |
2 |
100.00 |
IF |
223 |
2 |
2 |
100.00 |
IF |
231 |
5 |
5 |
100.00 |
CASE |
270 |
5 |
5 |
100.00 |
CASE |
282 |
6 |
6 |
100.00 |
IF |
320 |
4 |
4 |
100.00 |
IF |
330 |
3 |
3 |
100.00 |
IF |
365 |
4 |
4 |
100.00 |
IF |
434 |
2 |
2 |
100.00 |
IF |
498 |
4 |
2 |
50.00 |
IF |
580 |
2 |
2 |
100.00 |
IF |
586 |
5 |
3 |
60.00 |
IF |
595 |
3 |
3 |
100.00 |
IF |
753 |
2 |
2 |
100.00 |
CASE |
774 |
5 |
5 |
100.00 |
IF |
816 |
2 |
2 |
100.00 |
IF |
844 |
4 |
4 |
100.00 |
IF |
851 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 421 (fifo_full) ?
-2-: 421 (fifo_empty_negedge) ?
-3-: 421 ((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 431 (fifo_empty_gate) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T6,T19 |
LineNo. Expression
-1-: 494 ((hmac_fifo_wsel && fifo_wready)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 case (done_state_q)
-2-: 148 if (sha_hash_process)
-3-: 151 if (reg_hash_stop)
-4-: 158 if (reg_hash_done)
-5-: 165 if ((sha_message_length[8:0] == '0))
-6-: 173 if ((!hash_running))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
DoneAwaitCmd |
1 |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitCmd |
0 |
1 |
- |
- |
- |
Not Covered |
|
DoneAwaitCmd |
0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
DoneAwaitHashDone |
- |
- |
1 |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitHashDone |
- |
- |
0 |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete |
- |
- |
- |
1 |
- |
Not Covered |
|
DoneAwaitMessageComplete |
- |
- |
- |
0 |
- |
Not Covered |
|
DoneAwaitHashComplete |
- |
- |
- |
- |
1 |
Not Covered |
|
DoneAwaitHashComplete |
- |
- |
- |
- |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 184 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 197 if (wipe_secret)
-2-: 199 if ((!cfg_block))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T11,T14 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 210 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 223 if ((i < 8))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 231 if ((digest_size == SHA2_256))
-2-: 232 if ((i < 8))
-3-: 241 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-: 242 if ((((i % 2) == 0) && (i < 15)))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
1 |
- |
- |
Covered |
T1,T3,T4 |
1 |
0 |
- |
- |
Covered |
T1,T3,T4 |
0 |
- |
1 |
1 |
Covered |
T1,T4,T14 |
0 |
- |
1 |
0 |
Covered |
T1,T4,T14 |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 270 case (digest_size_supplied)
Branches:
-1- | Status | Tests |
SHA2_256 |
Covered |
T1,T3,T4 |
SHA2_384 |
Covered |
T1,T16,T17 |
SHA2_512 |
Covered |
T4,T14,T15 |
SHA2_None |
Covered |
T1,T2,T3 |
default |
Covered |
T1,T4,T11 |
LineNo. Expression
-1-: 282 case (key_length_supplied)
Branches:
-1- | Status | Tests |
Key_128 |
Covered |
T26,T15,T7 |
Key_256 |
Covered |
T1,T2,T3 |
Key_384 |
Covered |
T27,T7,T28 |
Key_512 |
Covered |
T1,T4,T19 |
Key_1024 |
Covered |
T29,T17,T7 |
default |
Covered |
T1,T4,T11 |
LineNo. Expression
-1-: 320 if ((!rst_ni))
-2-: 322 if (hash_start_or_continue)
-3-: 324 if ((reg_hash_done || reg_hash_stop))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 330 if ((!rst_ni))
-2-: 358 if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 365 if ((!rst_ni))
-2-: 367 if (hash_start_or_continue)
-3-: 369 if (packer_flush_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 434 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 498 if (hmac_fifo_wsel)
-2-: 500 if ((digest_size == SHA2_256))
-3-: 503 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T3,T4 |
1 |
0 |
1 |
Not Covered |
|
1 |
0 |
0 |
Not Covered |
|
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 580 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 586 if ((!cfg_block))
-2-: 587 if (reg2hw.msg_length_lower.qe)
-3-: 590 if (reg2hw.msg_length_upper.qe)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Not Covered |
|
1 |
0 |
- |
Covered |
T1,T2,T3 |
1 |
- |
1 |
Not Covered |
|
1 |
- |
0 |
Covered |
T1,T2,T3 |
0 |
- |
- |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 595 if (hash_start)
-2-: 597 if (((msg_write && sha_en) && packer_ready))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T3,T4 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 753 if (cfg_block)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 774 case (1'b1)
Branches:
-1- | Status | Tests |
hash_start_sha_disabled |
Covered |
T1,T4,T11 |
update_seckey_inprocess |
Covered |
T1,T4,T18 |
hash_start_active |
Covered |
T1,T4,T11 |
msg_push_not_allowed |
Covered |
T1,T4,T11 |
default |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 816 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 844 if ((!rst_ni))
-2-: 845 if (reg_hash_process)
-3-: 846 if (reg_hash_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 851 if ((!rst_ni))
-2-: 852 if (hash_start_or_continue)
-3-: 853 if (reg_hash_process)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
hmac
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
110 |
0 |
0 |
T11 |
100515 |
0 |
0 |
0 |
T14 |
455893 |
0 |
0 |
0 |
T24 |
6474 |
20 |
0 |
0 |
T31 |
0 |
30 |
0 |
0 |
T32 |
0 |
20 |
0 |
0 |
T33 |
0 |
20 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
3159 |
0 |
0 |
0 |
T36 |
165272 |
0 |
0 |
0 |
T37 |
12480 |
0 |
0 |
0 |
T38 |
44365 |
0 |
0 |
0 |
T39 |
4880 |
0 |
0 |
0 |
T40 |
41636 |
0 |
0 |
0 |
T41 |
783116 |
0 |
0 |
0 |
IntrFifoEmptyOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
IntrHmacDoneOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
TlOAReadyKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
TlODValidKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
ValidHashProcessAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
45566 |
0 |
0 |
T1 |
162797 |
7 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
41 |
0 |
0 |
T4 |
848063 |
192 |
0 |
0 |
T5 |
181849 |
48 |
0 |
0 |
T6 |
135069 |
38 |
0 |
0 |
T18 |
289075 |
194 |
0 |
0 |
T19 |
201321 |
57 |
0 |
0 |
T20 |
0 |
12 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
17 |
0 |
0 |
T42 |
0 |
32 |
0 |
0 |
ValidHmacEnConditionAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
11357 |
0 |
0 |
T1 |
162797 |
16 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
22 |
0 |
0 |
T4 |
848063 |
75 |
0 |
0 |
T5 |
181849 |
1 |
0 |
0 |
T6 |
135069 |
15 |
0 |
0 |
T18 |
289075 |
0 |
0 |
0 |
T19 |
201321 |
21 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
ValidWriteAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[0].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[1].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[2].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[3].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
Line Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
TOTAL | | 184 | 173 | 94.02 |
CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
ALWAYS | 143 | 15 | 9 | 60.00 |
ALWAYS | 184 | 3 | 3 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
ALWAYS | 196 | 7 | 7 | 100.00 |
ALWAYS | 210 | 3 | 3 | 100.00 |
ALWAYS | 221 | 0 | 0 | |
ALWAYS | 221 | 21 | 21 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
ALWAYS | 270 | 5 | 5 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
ALWAYS | 282 | 6 | 6 | 100.00 |
CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 306 | 1 | 1 | 100.00 |
CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
ALWAYS | 320 | 6 | 6 | 100.00 |
ALWAYS | 330 | 4 | 4 | 100.00 |
ALWAYS | 365 | 6 | 6 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
ALWAYS | 434 | 5 | 5 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
CONT_ASSIGN | 484 | 1 | 1 | 100.00 |
CONT_ASSIGN | 489 | 1 | 1 | 100.00 |
CONT_ASSIGN | 490 | 1 | 1 | 100.00 |
CONT_ASSIGN | 492 | 1 | 1 | 100.00 |
CONT_ASSIGN | 493 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
ALWAYS | 498 | 8 | 5 | 62.50 |
CONT_ASSIGN | 567 | 1 | 1 | 100.00 |
ALWAYS | 572 | 3 | 3 | 100.00 |
ALWAYS | 580 | 3 | 3 | 100.00 |
ALWAYS | 585 | 10 | 8 | 80.00 |
CONT_ASSIGN | 602 | 1 | 1 | 100.00 |
CONT_ASSIGN | 603 | 1 | 1 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 611 | 1 | 1 | 100.00 |
CONT_ASSIGN | 719 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 748 | 1 | 1 | 100.00 |
CONT_ASSIGN | 749 | 1 | 1 | 100.00 |
ALWAYS | 752 | 6 | 6 | 100.00 |
CONT_ASSIGN | 768 | 1 | 1 | 100.00 |
ALWAYS | 773 | 6 | 6 | 100.00 |
CONT_ASSIGN | 810 | 1 | 1 | 100.00 |
CONT_ASSIGN | 814 | 1 | 1 | 100.00 |
ALWAYS | 816 | 3 | 3 | 100.00 |
CONT_ASSIGN | 822 | 1 | 1 | 100.00 |
ALWAYS | 844 | 6 | 6 | 100.00 |
ALWAYS | 851 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
146 |
1 |
1 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
0 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
|
|
|
MISSING_ELSE |
165 |
0 |
1 |
168 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
173 |
0 |
1 |
174 |
0 |
1 |
175 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
210 |
2 |
2 |
211 |
1 |
1 |
221 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
239 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
|
|
|
MISSING_ELSE |
261 |
1 |
1 |
265 |
1 |
1 |
266 |
1 |
1 |
268 |
1 |
1 |
270 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
280 |
1 |
1 |
282 |
1 |
1 |
283 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
287 |
1 |
1 |
293 |
1 |
1 |
294 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
303 |
1 |
1 |
304 |
1 |
1 |
305 |
1 |
1 |
306 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
330 |
1 |
1 |
331 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
|
|
|
MISSING_ELSE |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
|
|
|
MISSING_ELSE |
414 |
1 |
1 |
421 |
1 |
1 |
429 |
1 |
1 |
431 |
1 |
1 |
434 |
1 |
1 |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
475 |
1 |
1 |
478 |
1 |
1 |
484 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
492 |
1 |
1 |
493 |
1 |
1 |
494 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
500 |
1 |
1 |
502 |
1 |
1 |
503 |
0 |
1 |
505 |
0 |
1 |
506 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
509 |
1 |
1 |
567 |
1 |
1 |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
580 |
2 |
2 |
581 |
1 |
1 |
585 |
1 |
1 |
586 |
1 |
1 |
587 |
1 |
1 |
588 |
0 |
1 |
|
|
|
MISSING_ELSE |
590 |
1 |
1 |
591 |
0 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
595 |
1 |
1 |
596 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
610 |
1 |
1 |
611 |
1 |
1 |
719 |
1 |
1 |
747 |
1 |
1 |
748 |
1 |
1 |
749 |
1 |
1 |
752 |
1 |
1 |
753 |
1 |
1 |
754 |
1 |
1 |
755 |
1 |
1 |
756 |
1 |
1 |
|
|
|
MISSING_ELSE |
760 |
1 |
1 |
768 |
1 |
1 |
773 |
1 |
1 |
774 |
1 |
1 |
776 |
1 |
1 |
780 |
1 |
1 |
784 |
1 |
1 |
788 |
1 |
1 |
810 |
1 |
1 |
814 |
1 |
1 |
816 |
1 |
1 |
817 |
1 |
1 |
819 |
1 |
1 |
822 |
1 |
1 |
844 |
2 |
2 |
845 |
2 |
2 |
846 |
2 |
2 |
|
|
|
MISSING_ELSE |
851 |
2 |
2 |
852 |
2 |
2 |
853 |
2 |
2 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut
| Total | Covered | Percent |
Conditions | 132 | 102 | 77.27 |
Logical | 132 | 102 | 77.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 165
EXPRESSION (sha_message_length[8:0] == '0)
---------------1---------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 231
EXPRESSION (digest_size == SHA2_256)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 241
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T14,T15 |
1 | 0 | Covered | T1,T16,T17 |
LINE 241
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T16,T17 |
LINE 241
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T14,T15 |
LINE 242
EXPRESSION (((i % 2) == 0) && (i < 15))
-------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T14 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T14 |
LINE 242
SUB-EXPRESSION ((i % 2) == 0)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T4,T14 |
1 | Covered | T1,T4,T14 |
LINE 248
EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
---------1--------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T14 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 254
EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
---------1--------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T14 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 303
EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
------------1----------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 304
EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
-----------1----------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Not Covered | |
LINE 305
EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
-------------1------------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Not Covered | |
LINE 306
EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
-------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 315
EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)))
-------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T4,T11 |
1 | 1 | 0 | Covered | T1,T4,T11 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 316
EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)))
--------1-------- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 317
EXPRESSION (hash_start | hash_continue)
-----1---- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 324
EXPRESSION (reg_hash_done || reg_hash_stop)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 358
EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
-------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 414
EXPRESSION (fifo_empty_q & ((~fifo_empty)))
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 421
EXPRESSION
Number Term
1 fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 421
SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 421
SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 421
SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
-------1------ --------2-------- --------3------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Covered | T1,T3,T4 |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 429
EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T19 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 431
EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
-------1-------
-1- | Status | Tests |
0 | Covered | T4,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 475
EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
------1----- --------2-------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 478
EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
------1----- ---------2--------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | T6,T19,T20 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 494
EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 494
SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
-------1------ -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 500
EXPRESSION (digest_size == SHA2_256)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T3,T4 |
LINE 503
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 503
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 503
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 519
EXPRESSION (fifo_wvalid & sha_en)
-----1----- ---2--
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T3,T4 |
LINE 567
EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
------1----- -----2----- ---------3--------- -----4-----
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | 0 | Covered | T1,T4,T11 |
1 | 1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 597
EXPRESSION (msg_write && sha_en && packer_ready)
----1---- ---2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | T6,T19,T20 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 617
EXPRESSION (msg_write & sha_en)
----1---- ---2--
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T3,T4 |
LINE 617
EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
-----1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 719
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T21,T22 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T23,T21 |
LINE 747
EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
------------------1----------------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 747
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 748
EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
------------------1----------------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 748
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
LINE 749
EXPRESSION (msg_fifo_req & ((~msg_allowed)))
------1----- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T4,T11 |
LINE 768
EXPRESSION (((~reg2hw.intr_state.hmac_err.q)) & (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed))
----------------1---------------- -----------------------------------------------2----------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T18 |
LINE 768
SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed)
-----------1----------- -----------2----------- --------3-------- ----------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T1,T4,T11 |
0 | 0 | 1 | 0 | Covered | T1,T4,T11 |
0 | 1 | 0 | 0 | Covered | T1,T4,T18 |
1 | 0 | 0 | 0 | Covered | T1,T4,T11 |
LINE 810
EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
----------1--------- --------2------- -------3------ ------4------
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
Toggle Coverage for Instance : tb.dut
| Total | Covered | Percent |
Totals |
30 |
30 |
100.00 |
Total Bits |
346 |
346 |
100.00 |
Total Bits 0->1 |
173 |
173 |
100.00 |
Total Bits 1->0 |
173 |
173 |
100.00 |
| | | |
Ports |
30 |
30 |
100.00 |
Port Bits |
346 |
346 |
100.00 |
Port Bits 0->1 |
173 |
173 |
100.00 |
Port Bits 1->0 |
173 |
173 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T19,T24 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T18,T20 |
Yes |
T4,T18,T20 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T4,T11,T7 |
Yes |
T4,T11,T7 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T23,T24 |
Yes |
T2,T23,T24 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T23,T24 |
Yes |
T2,T23,T24 |
OUTPUT |
intr_hmac_done_o |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
intr_fifo_empty_o |
Yes |
Yes |
T4,T25,T11 |
Yes |
T4,T25,T11 |
OUTPUT |
intr_hmac_err_o |
Yes |
Yes |
T1,T4,T18 |
Yes |
T1,T4,T18 |
OUTPUT |
idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T4 |
OUTPUT |
*Tests covering at least one bit in the range
FSM Coverage for Instance : tb.dut
Summary for FSM :: done_state_q
| Total | Covered | Percent | |
States |
4 |
2 |
50.00 |
(Not included in score) |
Transitions |
5 |
2 |
40.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: done_state_q
states | Line No. | Covered | Tests |
DoneAwaitCmd |
160 |
Covered |
T1,T2,T3 |
DoneAwaitHashComplete |
168 |
Not Covered |
|
DoneAwaitHashDone |
150 |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete |
153 |
Not Covered |
|
transitions | Line No. | Covered | Tests |
DoneAwaitCmd->DoneAwaitHashDone |
150 |
Covered |
T1,T3,T4 |
DoneAwaitCmd->DoneAwaitMessageComplete |
153 |
Not Covered |
|
DoneAwaitHashComplete->DoneAwaitCmd |
175 |
Not Covered |
|
DoneAwaitHashDone->DoneAwaitCmd |
160 |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete->DoneAwaitHashComplete |
168 |
Not Covered |
|
Branch Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
Branches |
|
87 |
77 |
88.51 |
TERNARY |
421 |
4 |
4 |
100.00 |
TERNARY |
431 |
2 |
2 |
100.00 |
TERNARY |
494 |
2 |
2 |
100.00 |
CASE |
146 |
10 |
4 |
40.00 |
IF |
184 |
2 |
2 |
100.00 |
IF |
197 |
3 |
3 |
100.00 |
IF |
210 |
2 |
2 |
100.00 |
IF |
223 |
2 |
2 |
100.00 |
IF |
231 |
5 |
5 |
100.00 |
CASE |
270 |
5 |
5 |
100.00 |
CASE |
282 |
6 |
6 |
100.00 |
IF |
320 |
4 |
4 |
100.00 |
IF |
330 |
3 |
3 |
100.00 |
IF |
365 |
4 |
4 |
100.00 |
IF |
434 |
2 |
2 |
100.00 |
IF |
498 |
4 |
2 |
50.00 |
IF |
580 |
2 |
2 |
100.00 |
IF |
586 |
5 |
3 |
60.00 |
IF |
595 |
3 |
3 |
100.00 |
IF |
753 |
2 |
2 |
100.00 |
CASE |
774 |
5 |
5 |
100.00 |
IF |
816 |
2 |
2 |
100.00 |
IF |
844 |
4 |
4 |
100.00 |
IF |
851 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 421 (fifo_full) ?
-2-: 421 (fifo_empty_negedge) ?
-3-: 421 ((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 431 (fifo_empty_gate) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T6,T19 |
LineNo. Expression
-1-: 494 ((hmac_fifo_wsel && fifo_wready)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 case (done_state_q)
-2-: 148 if (sha_hash_process)
-3-: 151 if (reg_hash_stop)
-4-: 158 if (reg_hash_done)
-5-: 165 if ((sha_message_length[8:0] == '0))
-6-: 173 if ((!hash_running))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
DoneAwaitCmd |
1 |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitCmd |
0 |
1 |
- |
- |
- |
Not Covered |
|
DoneAwaitCmd |
0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
DoneAwaitHashDone |
- |
- |
1 |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitHashDone |
- |
- |
0 |
- |
- |
Covered |
T1,T3,T4 |
DoneAwaitMessageComplete |
- |
- |
- |
1 |
- |
Not Covered |
|
DoneAwaitMessageComplete |
- |
- |
- |
0 |
- |
Not Covered |
|
DoneAwaitHashComplete |
- |
- |
- |
- |
1 |
Not Covered |
|
DoneAwaitHashComplete |
- |
- |
- |
- |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 184 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 197 if (wipe_secret)
-2-: 199 if ((!cfg_block))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T11,T14 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 210 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 223 if ((i < 8))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 231 if ((digest_size == SHA2_256))
-2-: 232 if ((i < 8))
-3-: 241 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-4-: 242 if ((((i % 2) == 0) && (i < 15)))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
1 |
- |
- |
Covered |
T1,T3,T4 |
1 |
0 |
- |
- |
Covered |
T1,T3,T4 |
0 |
- |
1 |
1 |
Covered |
T1,T4,T14 |
0 |
- |
1 |
0 |
Covered |
T1,T4,T14 |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 270 case (digest_size_supplied)
Branches:
-1- | Status | Tests |
SHA2_256 |
Covered |
T1,T3,T4 |
SHA2_384 |
Covered |
T1,T16,T17 |
SHA2_512 |
Covered |
T4,T14,T15 |
SHA2_None |
Covered |
T1,T2,T3 |
default |
Covered |
T1,T4,T11 |
LineNo. Expression
-1-: 282 case (key_length_supplied)
Branches:
-1- | Status | Tests |
Key_128 |
Covered |
T26,T15,T7 |
Key_256 |
Covered |
T1,T2,T3 |
Key_384 |
Covered |
T27,T7,T28 |
Key_512 |
Covered |
T1,T4,T19 |
Key_1024 |
Covered |
T29,T17,T7 |
default |
Covered |
T1,T4,T11 |
LineNo. Expression
-1-: 320 if ((!rst_ni))
-2-: 322 if (hash_start_or_continue)
-3-: 324 if ((reg_hash_done || reg_hash_stop))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 330 if ((!rst_ni))
-2-: 358 if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 365 if ((!rst_ni))
-2-: 367 if (hash_start_or_continue)
-3-: 369 if (packer_flush_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 434 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 498 if (hmac_fifo_wsel)
-2-: 500 if ((digest_size == SHA2_256))
-3-: 503 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T3,T4 |
1 |
0 |
1 |
Not Covered |
|
1 |
0 |
0 |
Not Covered |
|
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 580 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 586 if ((!cfg_block))
-2-: 587 if (reg2hw.msg_length_lower.qe)
-3-: 590 if (reg2hw.msg_length_upper.qe)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Not Covered |
|
1 |
0 |
- |
Covered |
T1,T2,T3 |
1 |
- |
1 |
Not Covered |
|
1 |
- |
0 |
Covered |
T1,T2,T3 |
0 |
- |
- |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 595 if (hash_start)
-2-: 597 if (((msg_write && sha_en) && packer_ready))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T3,T4 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 753 if (cfg_block)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 774 case (1'b1)
Branches:
-1- | Status | Tests |
hash_start_sha_disabled |
Covered |
T1,T4,T11 |
update_seckey_inprocess |
Covered |
T1,T4,T18 |
hash_start_active |
Covered |
T1,T4,T11 |
msg_push_not_allowed |
Covered |
T1,T4,T11 |
default |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 816 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 844 if ((!rst_ni))
-2-: 845 if (reg_hash_process)
-3-: 846 if (reg_hash_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 851 if ((!rst_ni))
-2-: 852 if (hash_start_or_continue)
-3-: 853 if (reg_hash_process)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
110 |
0 |
0 |
T11 |
100515 |
0 |
0 |
0 |
T14 |
455893 |
0 |
0 |
0 |
T24 |
6474 |
20 |
0 |
0 |
T31 |
0 |
30 |
0 |
0 |
T32 |
0 |
20 |
0 |
0 |
T33 |
0 |
20 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
3159 |
0 |
0 |
0 |
T36 |
165272 |
0 |
0 |
0 |
T37 |
12480 |
0 |
0 |
0 |
T38 |
44365 |
0 |
0 |
0 |
T39 |
4880 |
0 |
0 |
0 |
T40 |
41636 |
0 |
0 |
0 |
T41 |
783116 |
0 |
0 |
0 |
IntrFifoEmptyOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
IntrHmacDoneOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
TlOAReadyKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
TlODValidKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
387894521 |
0 |
0 |
T1 |
162797 |
162713 |
0 |
0 |
T2 |
1253 |
1155 |
0 |
0 |
T3 |
837031 |
836977 |
0 |
0 |
T4 |
848063 |
847952 |
0 |
0 |
T5 |
181849 |
181798 |
0 |
0 |
T6 |
135069 |
134974 |
0 |
0 |
T18 |
289075 |
289067 |
0 |
0 |
T19 |
201321 |
201094 |
0 |
0 |
T23 |
1192 |
1116 |
0 |
0 |
T30 |
57185 |
57133 |
0 |
0 |
ValidHashProcessAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
45566 |
0 |
0 |
T1 |
162797 |
7 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
41 |
0 |
0 |
T4 |
848063 |
192 |
0 |
0 |
T5 |
181849 |
48 |
0 |
0 |
T6 |
135069 |
38 |
0 |
0 |
T18 |
289075 |
194 |
0 |
0 |
T19 |
201321 |
57 |
0 |
0 |
T20 |
0 |
12 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
17 |
0 |
0 |
T42 |
0 |
32 |
0 |
0 |
ValidHmacEnConditionAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
11357 |
0 |
0 |
T1 |
162797 |
16 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
22 |
0 |
0 |
T4 |
848063 |
75 |
0 |
0 |
T5 |
181849 |
1 |
0 |
0 |
T6 |
135069 |
15 |
0 |
0 |
T18 |
289075 |
0 |
0 |
0 |
T19 |
201321 |
21 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
ValidWriteAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[0].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[1].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[2].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |
gen_assert_wmask_bytealign[3].unnamed$$_0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387966381 |
26228374 |
0 |
0 |
T1 |
162797 |
16258 |
0 |
0 |
T2 |
1253 |
0 |
0 |
0 |
T3 |
837031 |
30579 |
0 |
0 |
T4 |
848063 |
76962 |
0 |
0 |
T5 |
181849 |
31649 |
0 |
0 |
T6 |
135069 |
79117 |
0 |
0 |
T18 |
289075 |
74233 |
0 |
0 |
T19 |
201321 |
84019 |
0 |
0 |
T20 |
0 |
21060 |
0 |
0 |
T23 |
1192 |
0 |
0 |
0 |
T30 |
57185 |
9645 |
0 |
0 |
T42 |
0 |
39652 |
0 |
0 |