Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.92	95.33	79.55		100.00	84.81

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	89.92	95.33	79.55		100.00	84.81

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.92	95.33	79.55		100.00	84.81

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.92	95.33	79.55		100.00	84.81

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.30	94.02	77.27	100.00	40.00	88.51	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		150	143	95.33
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
ALWAYS	132	21	21	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	211	16	15	93.75
CONT_ASSIGN	235	1	1	100.00
ALWAYS	238	4	4	100.00
CONT_ASSIGN	246	1	1	100.00
ALWAYS	254	10	6	60.00
ALWAYS	272	3	3	100.00
ALWAYS	278	6	6	100.00
ALWAYS	288	4	4	100.00
ALWAYS	296	6	6	100.00
CONT_ASSIGN	305	1	1	100.00
ALWAYS	308	3	3	100.00
ALWAYS	313	64	62	96.88
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
122	1	1
124	1	1
125	1	1
127	1	1
128	1	1
132	1	1
134	1	1
136	1	1
138	1	1
140	1	1
144	1	1
146	1	1
148	1	1
150	1	1
154	1	1
156	1	1
158	1	1
160	1	1
164	1	1
165	1	1
167	1	1
168	1	1
173	1	1
174	1	1
176	1	1
177	1	1
192	1	1
194	1	1
195	1	1
211	1	1
212	1	1
213	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
222	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
232	0	1
235	1	1
238	1	1
239	1	1
240	1	1
241	1	1
246	1	1
254	1	1
255	1	1
256	1	1
257	1	1
260	0	1
261	0	1
262	0	1
263	0	1
266	1	1
267	1	1
			MISSING_ELSE
272	2	2
273	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
			MISSING_ELSE
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
			==> MISSING_ELSE
305	1	1
308	2	2
309	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
329	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
337	1	1
342	1	1
344	1	1
345	1	1
347	1	1
349	1	1
351	1	1
356	1	1
357	1	1
359	1	1
360	0	1
361	0	1
			MISSING_ELSE
364	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
376	1	1
378	1	1
379	1	1
380	1	1
382	1	1
385	1	1
390	1	1
391	1	1
392	1	1
393	1	1
395	1	1
399	1	1
401	1	1
402	1	1
403	1	1
404	1	1
406	1	1
412	1	1
413	1	1
415	1	1
416	1	1
418	1	1
420	1	1
422	1	1
428	1	1
430	1	1
442	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	176	140	79.55
Logical	176	140	79.55
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       122
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       124
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       125
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       192
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       192
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       194
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Not Covered
1	1	Not Covered

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       195
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T14,T45,T7
1	0	Covered	T1,T15,T7

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T15,T7

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T45,T7

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Not Covered
1	1	Not Covered

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       195
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T14,T45,T7
1	0	Covered	T1,T15,T7

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T15,T7

 LINE       195
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T45,T7

 LINE       195
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       195
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       216
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       217
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T46,T47
1	Covered	T1,T3,T4

 LINE       219
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T46,T47
0	1	Covered	T28,T48,T49
1	0	Covered	T1,T50

 LINE       219
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T46,T47
1	Covered	T1,T50

 LINE       219
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T46,T47
1	Covered	T28,T48,T49

 LINE       222
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       224
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T3,T4

 LINE       226
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T15,T7,T28

 LINE       228
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T14,T45,T7

 LINE       239
 EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       240
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T16,T17
1	Covered	T51

 LINE       241
 EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T14,T15
1	Not Covered

 LINE       246
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       282
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       300
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       305
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       305
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       357
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       359
 EXPRESSION ((round_q == Inner) && reg_hash_continue_i)
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       359
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       364
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       364
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       364
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       364
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       364
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       368
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       379
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       395
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       395
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T3,T4

 LINE       395
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       395
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       395
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       395
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       395
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       395
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       395
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       395
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       395
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       442
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start_i || reg_hash_continue_i) ))
             --------1-------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION ( ! (reg_hash_start_i || reg_hash_continue_i) )
                    --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       442
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	380	Covered	T1,T3,T4
StIPad	330	Covered	T1,T3,T4
StIdle	337	Covered	T1,T2,T3
StMsg	345	Covered	T1,T3,T4
StOPad	399	Covered	T1,T3,T4
StPushToMsgFifo	382	Covered	T1,T3,T4
StWaitResp	366	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	428	Covered	T1,T3,T4
StIPad->StMsg	345	Covered	T1,T3,T4
StIdle->StIPad	330	Covered	T1,T3,T4
StMsg->StWaitResp	366	Covered	T1,T3,T4
StOPad->StMsg	416	Covered	T1,T3,T4
StPushToMsgFifo->StOPad	399	Covered	T1,T3,T4
StWaitResp->StDone	380	Covered	T1,T3,T4
StWaitResp->StPushToMsgFifo	382	Covered	T1,T3,T4

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		79	67	84.81
TERNARY	121	2	2	100.00
TERNARY	122	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	125	2	2	100.00
TERNARY	192	2	2	100.00
TERNARY	194	2	2	100.00
TERNARY	195	7	4	57.14
TERNARY	305	2	2	100.00
CASE	132	6	5	83.33
IF	212	9	8	88.89
CASE	238	4	4	100.00
IF	255	7	3	42.86
IF	272	2	2	100.00
IF	278	4	4	100.00
IF	288	3	3	100.00
IF	296	4	3	75.00
IF	308	2	2	100.00
CASE	327	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	121	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	((!hmac_en_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	195	((!hmac_en_i)) ? 
-2-:	195	(((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? 
-3-:	195	(((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-4-:	195	(((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? 
-5-:	195	(((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-6-:	195	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T3,T4
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	305	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	132	case (key_length_i)

Branches:

-1-	Status	Tests
Key_128	Covered	T26,T15,T7
Key_256	Covered	T1,T2,T3
Key_384	Covered	T27,T7,T28
Key_512	Covered	T1,T4,T19
Key_1024	Covered	T29,T17,T7
default	Not Covered

	LineNo.	Expression
-1-:	212	if ((!hmac_en_i))
-2-:	216	if ((sel_msglen == SelIPadMsg))
-3-:	217	if ((digest_size_i == SHA2_256))
-4-:	219	if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
-5-:	222	if ((sel_msglen == SelOPadMsg))
-6-:	224	if ((digest_size_i == SHA2_256))
-7-:	226	if ((digest_size_i == SHA2_384))
-8-:	228	if ((digest_size_i == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T3,T4
0	1	0	1	-	-	-	-	Covered	T1,T28,T50
0	1	0	0	-	-	-	-	Covered	T1,T46,T47
0	0	-	-	1	1	-	-	Covered	T1,T3,T4
0	0	-	-	1	0	1	-	Covered	T15,T7,T28
0	0	-	-	1	0	0	1	Covered	T14,T45,T7
0	0	-	-	1	0	0	0	Covered	T1,T4,T11
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	238	case (digest_size_i)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T3,T4
SHA2_384	Covered	T1,T16,T17
SHA2_512	Covered	T4,T14,T15
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	if (clr_txcount)
-2-:	257	if (load_txcount)
-3-:	260	case (digest_size_i)
-4-:	266	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T3,T4
0	1	SHA2_256	-	Not Covered
0	1	SHA2_384	-	Not Covered
0	1	SHA2_512	-	Not Covered
0	1	default	-	Not Covered
0	0	-	1	Covered	T1,T3,T4
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))
-2-:	280	if (reg_hash_process_i)
-3-:	282	if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))
-2-:	290	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	296	if ((!rst_ni))
-2-:	298	if (clr_fifo_wdata_sel)
-3-:	300	if ((fifo_wsel_o && fifo_wvalid_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	308	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	case (st_q)
-2-:	329	if ((hmac_en_i && reg_hash_start_i))
-3-:	344	if (txcnt_eq_blksz)
-4-:	359	if (((round_q == Inner) && reg_hash_continue_i))
-5-:	364	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o)))
-6-:	378	if (sha_hash_done_i)
-7-:	379	if ((round_q == Outer))
-8-:	395	if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))))
-9-:	415	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T1,T3,T4
StIPad	-	0	-	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	1	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	0	-	-	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	0	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	0	-	-	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
StDone	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	Not Covered