Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215459342	627926	0	0
intr_enable_rd_A	215459342	2802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215459342	627926	0	0
T8	495913	216688	0	0
T20	0	67191	0	0
T21	0	924	0	0
T22	3177	0	0	0
T46	16269	0	0	0
T47	51224	0	0	0
T48	33333	0	0	0
T50	0	1	0	0
T51	0	2	0	0
T56	0	598	0	0
T57	0	7	0	0
T60	0	8	0	0
T61	0	432	0	0
T62	0	271	0	0
T63	21165	0	0	0
T64	188951	0	0	0
T65	784007	0	0	0
T66	3022	0	0	0
T67	20246	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215459342	2802	0	0
T19	0	24	0	0
T22	3177	36	0	0
T47	51224	0	0	0
T48	33333	0	0	0
T49	55102	0	0	0
T58	0	9	0	0
T63	21165	0	0	0
T64	188951	0	0	0
T65	784007	0	0	0
T66	3022	0	0	0
T67	20246	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	0	52	0	0
T71	0	43	0	0
T72	0	11	0	0
T73	0	15	0	0
T74	0	26	0	0
T75	213314	0	0	0