SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 28014260 | 1 | T1 | 3983 | T2 | 252 | T3 | 315816 | ||||
auto[1] | 11213954 | 1 | T1 | 507 | T2 | 48 | T3 | 74389 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39227972 | 1 | T1 | 4490 | T2 | 300 | T3 | 390205 | ||||
values[1] | 26 | 1 | T50 | 1 | T52 | 1 | T105 | 1 | ||||
values[2] | 6 | 1 | T106 | 1 | T107 | 2 | T108 | 1 | ||||
values[3] | 115 | 1 | T50 | 5 | T51 | 5 | T52 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39227991 | 1 | T1 | 4490 | T2 | 300 | T3 | 390205 | ||||
values[1] | 16 | 1 | T50 | 1 | T105 | 1 | T109 | 1 | ||||
values[2] | 3 | 1 | T105 | 1 | T109 | 1 | T110 | 1 | ||||
values[3] | 124 | 1 | T50 | 4 | T51 | 3 | T52 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 39227854 | 1 | T1 | 4490 | T2 | 300 | T3 | 390205 | ||||
auto[TlIntgErrCmd] | 137 | 1 | T50 | 2 | T51 | 5 | T52 | 5 | ||||
auto[TlIntgErrData] | 118 | 1 | T51 | 3 | T52 | 2 | T105 | 7 | ||||
auto[TlIntgErrBoth] | 105 | 1 | T50 | 8 | T51 | 2 | T52 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |