Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

19481541

1

T1

1743

T2

142

T3

191240

full_word

19746673

1

T1

2747

T2

158

T3

198965

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	39227854	1			T1	4490		T2	300		T3	390205
auto[TlIntgErrCmd]	137	1			T50	2		T51	5		T52	5
auto[TlIntgErrData]	118	1			T51	3		T52	2		T105	7
auto[TlIntgErrBoth]	105	1			T50	8		T51	2		T52	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15328958

1

T1

2167

T2

127

T3

157893

auto[1]

23899256

1

T1

2323

T2

173

T3

232312

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7911568	1			T1	1194		T2	64		T3	78890
auto[TlIntgErrNone]	partial	auto[1]	11569641	1			T1	549		T2	78		T3	112350
auto[TlIntgErrNone]	full_word	auto[0]	7417227	1			T1	973		T2	63		T3	79003
auto[TlIntgErrNone]	full_word	auto[1]	12329418	1			T1	1774		T2	95		T3	119962
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T51	2		T52	2		T105	3
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T50	2		T51	3		T52	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T105	1		T111	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T106	1		T112	1		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T51	1		T105	2		T106	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T51	2		T52	1		T105	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T109	1		T111	1		T108	3
auto[TlIntgErrData]	full_word	auto[1]	5	1			T52	1		T106	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T50	4		T52	1		T105	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T50	2		T51	2		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T106	1		T109	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T50	2		T105	1		T114	2