Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16162757

1

T1

62668

T2

19832

T3

105

full_word

16470101

1

T1

52029

T2

21295

T3

134

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32632458	1			T1	114697		T2	41127		T3	239
auto[TlIntgErrCmd]	147	1			T31	3		T53	8		T54	11
auto[TlIntgErrData]	115	1			T31	4		T53	7		T54	9
auto[TlIntgErrBoth]	138	1			T31	3		T53	15		T54	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12685135

1

T1

46069

T2

18207

T3

119

auto[1]

19947723

1

T1

68628

T2

22920

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6564730	1			T1	23116		T2	9147		T3	57
auto[TlIntgErrNone]	partial	auto[1]	9597655	1			T1	39552		T2	10685		T3	48
auto[TlIntgErrNone]	full_word	auto[0]	6120219	1			T1	22953		T2	9060		T3	62
auto[TlIntgErrNone]	full_word	auto[1]	10349854	1			T1	29076		T2	12235		T3	72
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T31	1		T53	5		T54	5
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T31	2		T53	3		T54	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T54	1		T122	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T118	1		T116	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T31	2		T53	6		T54	5
auto[TlIntgErrData]	partial	auto[1]	49	1			T31	1		T53	1		T54	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T54	1		T118	2		T122	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T31	1		T117	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T31	2		T53	3		T54	5
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T31	1		T53	11		T54	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T53	1		T118	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	1		T117	1		T119	1