Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	178214545	609085	0	0
intr_enable_rd_A	178214545	2861	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178214545	609085	0	0
T29	365274	108362	0	0
T30	0	324	0	0
T31	0	4	0	0
T52	0	408	0	0
T53	0	12	0	0
T55	0	674	0	0
T56	0	288266	0	0
T57	0	815	0	0
T58	0	419	0	0
T59	0	42861	0	0
T62	5624	0	0	0
T63	115620	0	0	0
T64	403783	0	0	0
T65	28840	0	0	0
T66	185652	0	0	0
T67	2982	0	0	0
T68	96650	0	0	0
T69	92599	0	0	0
T70	202235	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178214545	2861	0	0
T31	0	59	0	0
T33	427541	51	0	0
T50	102057	0	0	0
T61	0	60	0	0
T71	0	59	0	0
T72	0	19	0	0
T73	0	48	0	0
T74	0	9	0	0
T75	0	10	0	0
T76	0	16	0	0
T77	0	41	0	0
T78	117364	0	0	0
T79	6919	0	0	0
T80	944	0	0	0
T81	99176	0	0	0
T82	328794	0	0	0
T83	4923	0	0	0
T84	106863	0	0	0
T85	288592	0	0	0